From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BC5F2C433F5 for ; Mon, 7 Feb 2022 19:04:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=WOcmVsV8O0ywbGso+mW9ywFMiVqLnW+kVn70DhNpXqk=; b=c5TPKZ0EV0+gO0 dQL4bt4Iv0wNSU6hhZ0i5OFVQYJIb1+exijgpBGJ6LM0SP5wpfeRCSUbVnXAcLYeTHOBATswcg3Zl srJyWsnlD6a8hisqU7EykUJV3VQ/gjT1OwF8W7g8gsvMr3EGP43no3+4WQi6ru/clCJnQ29pr4GbW NFaG4LmWfYD11qUiuJoHMN9fLNHF6JQWUJZ5fizcG8eph4guKrAbNw83mis7bWCAJ1us/8/+qRo3p Q3CJ0jXyXZjExk/WT0o9Kqxom0IO8cz1NknG2LPBEDzGY5yRfJNKdCx80Bq316pScuiZqLM6j/Cq7 f56G5CkmRiLh9pbxQhpg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nH9IK-00BSMO-76; Mon, 07 Feb 2022 19:03:24 +0000 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nH9IF-00BSL8-TT for linux-arm-kernel@lists.infradead.org; Mon, 07 Feb 2022 19:03:21 +0000 Received: by mail-pj1-x102a.google.com with SMTP id t4-20020a17090a510400b001b8c4a6cd5dso54pjh.5 for ; Mon, 07 Feb 2022 11:03:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=zweFrYRkCzguHpFVOCBPGa3h4HNGTtGroD9vGrjNJbI=; b=ykQz/txh8PHkGPgZ8Ects4oRlUbvZXFBniPRUT6dXw4otCDVProVp3AgvdMT1QG7LE 9V42K9AVJIncDnBwtE9S36ZSauhRJb8rhD0ZjwoXqV+5VCGJB7Y5TyBsZYVIU19Hg4fN 1oOiUvZm/GM7DAtoRoUScPI4QWaX6iB22dF807RNkXRzzauWlKLXwdRkk4tvBJuvgib5 /D11AK+R2vEFZdmhtYaS87+7wfC6acratRbbv9G8wmAPedH3PFsUvL7ThphnIXB1Pr4r uyEiz0Ot0cXU5r64nNpx3KkuNC6iAannQ3JUAu/CZNVdZL1StCAMmcLxP2SS7wv/Zh4s 6AEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=zweFrYRkCzguHpFVOCBPGa3h4HNGTtGroD9vGrjNJbI=; b=gg/2vgV1tBfLEX3PAOvkBeXCzgpgf7sSRIlNX8pWLNLKD+cgSnXLjCSNtXOiACInmP ESuva6aqrgs5hntT3hpvlSRSXQbvbtMC4dfCwyjA/QJiOpRkKChZMcHnK17NZB+6ZClh Nob9pJgwQE1sLhN293f3c4hoze+elAulxv4jP4DIQ7p39hpnk+DQ2jt+dMuzKebQJWpX /9NOLAL44D7toC4PdAcl+AVAHl9N80bsbmTK38NUVXcFy70sdwz0Rv96nL8ci3APYq4T m1zKUhgxTie7vlW/Rv95NNGEca6TUFaZu/XUhh0GKpzja/x8ezyK/Okuhn533LqighfZ c9/A== X-Gm-Message-State: AOAM530pp/aHaTn2m8hyHZ0YrZF+aqRB23hJ88i/SGbyRue9Pf39uRJj KAWJ6RF5+v9DV9oiOuyH5AAWhw== X-Google-Smtp-Source: ABdhPJy2ruqmawn7O3pRdBnhzMLuaQ4nwJkyZuEtP+ONUhmVb96zPPlst8w9ZJm5eEaQ5FQebQOphw== X-Received: by 2002:a17:903:11c9:: with SMTP id q9mr726574plh.144.1644260598836; Mon, 07 Feb 2022 11:03:18 -0800 (PST) Received: from p14s (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id y41sm12964976pfa.213.2022.02.07.11.03.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Feb 2022 11:03:17 -0800 (PST) Date: Mon, 7 Feb 2022 12:03:15 -0700 From: Mathieu Poirier To: James Clark Cc: suzuki.poulose@arm.com, coresight@lists.linaro.org, leo.yan@linaro.com, mike.leach@linaro.org, Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 07/15] coresight: Make ETM4x TRCEVENTCTL1R register accesses consistent with sysreg.h Message-ID: <20220207190315.GC3355405@p14s> References: <20220203120604.128396-1-james.clark@arm.com> <20220203120604.128396-8-james.clark@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220203120604.128396-8-james.clark@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220207_110319_987058_675FD333 X-CRM114-Status: GOOD ( 20.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Feb 03, 2022 at 12:05:55PM +0000, James Clark wrote: > This is a no-op change for style and consistency and has no effect on the > binary produced by gcc-11. > > Signed-off-by: James Clark > --- > .../coresight/coresight-etm4x-sysfs.c | 25 +++++++++++-------- > drivers/hwtracing/coresight/coresight-etm4x.h | 9 +++++++ > 2 files changed, 24 insertions(+), 10 deletions(-) > I like what this patchset is doing. I have reviewed up to here today and will finish tomorrow. Thanks, Mathieu > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > index 4c29ab4464a0..cfa6f72a1e39 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > @@ -384,16 +384,16 @@ static ssize_t mode_store(struct device *dev, > /* bit[11], AMBA Trace Bus (ATB) trigger enable bit */ > if ((config->mode & ETM_MODE_ATB_TRIGGER) && > (drvdata->atbtrig == true)) > - config->eventctrl1 |= BIT(11); > + config->eventctrl1 |= TRCEVENTCTL1R_ATB; > else > - config->eventctrl1 &= ~BIT(11); > + config->eventctrl1 &= ~TRCEVENTCTL1R_ATB; > > /* bit[12], Low-power state behavior override bit */ > if ((config->mode & ETM_MODE_LPOVERRIDE) && > (drvdata->lpoverride == true)) > - config->eventctrl1 |= BIT(12); > + config->eventctrl1 |= TRCEVENTCTL1R_LPOVERRIDE; > else > - config->eventctrl1 &= ~BIT(12); > + config->eventctrl1 &= ~TRCEVENTCTL1R_LPOVERRIDE; > > /* bit[8], Instruction stall bit */ > if ((config->mode & ETM_MODE_ISTALL_EN) && (drvdata->stallctl == true)) > @@ -534,7 +534,7 @@ static ssize_t event_instren_show(struct device *dev, > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct etmv4_config *config = &drvdata->config; > > - val = BMVAL(config->eventctrl1, 0, 3); > + val = REG_VAL(config->eventctrl1, TRCEVENTCTL1R_INSTEN); > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > } > > @@ -551,23 +551,28 @@ static ssize_t event_instren_store(struct device *dev, > > spin_lock(&drvdata->spinlock); > /* start by clearing all instruction event enable bits */ > - config->eventctrl1 &= ~(BIT(0) | BIT(1) | BIT(2) | BIT(3)); > + config->eventctrl1 &= ~(TRCEVENTCTL1R_INSTEN_MASK << TRCEVENTCTL1R_INSTEN_SHIFT); > switch (drvdata->nr_event) { > case 0x0: > /* generate Event element for event 1 */ > - config->eventctrl1 |= val & BIT(1); > + config->eventctrl1 |= val & TRCEVENTCTL1R_INSTEN_1; > break; > case 0x1: > /* generate Event element for event 1 and 2 */ > - config->eventctrl1 |= val & (BIT(0) | BIT(1)); > + config->eventctrl1 |= val & (TRCEVENTCTL1R_INSTEN_0 | TRCEVENTCTL1R_INSTEN_1); > break; > case 0x2: > /* generate Event element for event 1, 2 and 3 */ > - config->eventctrl1 |= val & (BIT(0) | BIT(1) | BIT(2)); > + config->eventctrl1 |= val & (TRCEVENTCTL1R_INSTEN_0 | > + TRCEVENTCTL1R_INSTEN_1 | > + TRCEVENTCTL1R_INSTEN_2); > break; > case 0x3: > /* generate Event element for all 4 events */ > - config->eventctrl1 |= val & 0xF; > + config->eventctrl1 |= val & (TRCEVENTCTL1R_INSTEN_0 | > + TRCEVENTCTL1R_INSTEN_1 | > + TRCEVENTCTL1R_INSTEN_2 | > + TRCEVENTCTL1R_INSTEN_3); > break; > default: > break; > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index 55e756020a94..eb72b81bbf85 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -211,6 +211,15 @@ > #define TRCCONFIGR_DA BIT(16) > #define TRCCONFIGR_DV BIT(17) > > +#define TRCEVENTCTL1R_INSTEN_SHIFT 0 > +#define TRCEVENTCTL1R_INSTEN_MASK GENMASK(3, 0) > +#define TRCEVENTCTL1R_INSTEN_0 BIT(0) > +#define TRCEVENTCTL1R_INSTEN_1 BIT(1) > +#define TRCEVENTCTL1R_INSTEN_2 BIT(2) > +#define TRCEVENTCTL1R_INSTEN_3 BIT(3) > +#define TRCEVENTCTL1R_ATB BIT(11) > +#define TRCEVENTCTL1R_LPOVERRIDE BIT(12) > + > /* > * System instructions to access ETM registers. > * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions > -- > 2.28.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel