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[68.147.0.187]) by smtp.gmail.com with ESMTPSA id ip5sm3690253pjb.13.2022.02.08.10.58.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Feb 2022 10:58:16 -0800 (PST) Date: Tue, 8 Feb 2022 11:58:14 -0700 From: Mathieu Poirier To: James Clark Cc: suzuki.poulose@arm.com, coresight@lists.linaro.org, leo.yan@linaro.com, mike.leach@linaro.org, Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 15/15] coresight: Make ETM4x TRCRSCTLRn register accesses consistent with sysreg.h Message-ID: <20220208185814.GA3508773@p14s> References: <20220203120604.128396-1-james.clark@arm.com> <20220203120604.128396-16-james.clark@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220203120604.128396-16-james.clark@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220208_105819_616899_9193F6EE X-CRM114-Status: GOOD ( 18.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Feb 03, 2022 at 12:06:03PM +0000, James Clark wrote: > This is a no-op change for style and consistency and has no effect on the > binary produced by gcc-11. > > Signed-off-by: James Clark > --- > drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 7 +++++-- > drivers/hwtracing/coresight/coresight-etm4x.h | 9 +++++++++ > 2 files changed, 14 insertions(+), 2 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > index a0cdd2cd978a..c876a63fa84d 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > @@ -1728,8 +1728,11 @@ static ssize_t res_ctrl_store(struct device *dev, > /* For odd idx pair inversal bit is RES0 */ > if (idx % 2 != 0) > /* PAIRINV, bit[21] */ > - val &= ~BIT(21); > - config->res_ctrl[idx] = val & GENMASK(21, 0); > + val &= ~TRCRSCTLRn_PAIRINV; > + config->res_ctrl[idx] = val & (TRCRSCTLRn_PAIRINV | > + TRCRSCTLRn_INV | > + (TRCRSCTLRn_GROUP_MASK << TRCRSCTLRn_GROUP_SHIFT) | > + (TRCRSCTLRn_SELECT_MASK << TRCRSCTLRn_SELECT_SHIFT)); > spin_unlock(&drvdata->spinlock); > return size; > } > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index 4d943faade33..dd2156a5e70b 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -258,6 +258,15 @@ > #define TRCBBCTLR_RANGE_SHIFT 0 > #define TRCBBCTLR_RANGE_MASK GENMASK(7, 0) > > +#define TRCRSCTLRn_PAIRINV BIT(21) > +#define TRCRSCTLRn_INV BIT(20) > +#define TRCRSCTLRn_GROUP_SHIFT 16 > +#define TRCRSCTLRn_GROUP_MASK GENMASK(3, 0) > +#define TRCRSCTLRn_SELECT_SHIFT 0 > +#define TRCRSCTLRn_SELECT_MASK GENMASK(15, 0) > + > + > + Two extra newlines. With the above and for patches 02 to 15: Reviewed-by: Mathieu Poirier > /* > * System instructions to access ETM registers. > * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions > -- > 2.28.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel