From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F0C16C433EF for ; Thu, 10 Feb 2022 19:36:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:CC:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=j+FCXzG7BbiEMMY7pQExJ0jzOk1elzH+mxPwWhDU6aQ=; b=lpWbrlcXqCHq7d bYVDHJk2Ll6XOEiGwJttP2yft4VfN0vwZbrUMLo/d6MAprqTcqU7gbaoV+j6IiIFhCxe1oPniP9ZG mTKsGyrQmfqVQF93LBEAhbF/4KxkiO6wSHxcm82NbNYoT8CTMgMVuIxsIJp1JXZnj/8saGnYvQjIa In/lNyIx8q4I6Nh46c0uE7wbfWhjYvdoiHd22AK/RqzdHdksb+BqHRAwYyC2Dty3Q/qWjLWLH0mfa vl3AKw77AIgDB3crS+w54TEMJ/OUeSaP3E+KJFacxfCI/MwCHYquMiB2tTKRrMArm2eLxM00kH6Dm q0Gu8MNldidxJffSbXiw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nIFDk-004mIv-8N; Thu, 10 Feb 2022 19:35:12 +0000 Received: from lelv0142.ext.ti.com ([198.47.23.249]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nIFDf-004mHi-N4 for linux-arm-kernel@lists.infradead.org; Thu, 10 Feb 2022 19:35:10 +0000 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 21AJYxi7056840; Thu, 10 Feb 2022 13:34:59 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1644521699; bh=/bJ9iS5dwRmi3cHk4NArM1//+U9uqS5txh7CfIsrBUk=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=slO7lGXd+EMThj4PR2jsTrB2byPNkJgf6+5JQpgzVMeYZqWTWJ7cMDjzSUEXQtFj3 V8B+R06c3AV39wMEvdFlBED5YcuMeufp3yzeoxoIcDVcOTm0T5gcujyeT7fkwNnGno 4FVpqU0wg3KXGpuPRn3/RKENIM5lPRlrb+DE0sCw= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 21AJYxpL110267 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 10 Feb 2022 13:34:59 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Thu, 10 Feb 2022 13:34:59 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Thu, 10 Feb 2022 13:34:59 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 21AJYxmX064678; Thu, 10 Feb 2022 13:34:59 -0600 Date: Thu, 10 Feb 2022 13:34:59 -0600 From: Nishanth Menon To: Marc Zyngier CC: Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Santosh Shilimkar , , , Subject: Re: [PATCH 4/5] arm64: dts: ti: Introduce base support for AM62x SoC Message-ID: <20220210193459.nl6baranvmqs46bi@coastal> References: <20220208131827.1430086-1-vigneshr@ti.com> <20220208131827.1430086-5-vigneshr@ti.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20171215 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220210_113507_925913_FDDDFF4C X-CRM114-Status: GOOD ( 11.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 19:10-20220209, Marc Zyngier wrote: [...] > > +&cbass_main { > > + gic500: interrupt-controller@1800000 { > > + compatible = "arm,gic-v3"; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + #interrupt-cells = <3>; > > + interrupt-controller; > > + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ > > + <0x00 0x01880000 0x00 0xC0000>; /* GICR */ > > Usual rant: you are missing the GICC, GICH and GICV regions > that are implemented by the CPU. Cortex-A53 implements them > (they are not optional), so please describe them. > -ECONFUSED. TRM for GIC500 refers to just GICD, GICR and ITS range[1]. Same thing is indicated by Generic Interrupt Controller Architecture Specification[2] See table 1-1 (page 23). I think you are expecting GICV3's backward compatibility mode (Table 1-2 in page 24), But in K3 architecture, are_option meant for backward compatibility is set to true (aka no backward compatibility). I think this did popup sometime back as well (first k3 SoC)[3]. I think the more clearer description is available in [4]. I believe the argumentation that GICC/H/V is mandatory for A53 if GIC500 is used is not accurate. Please correct me if I am mistaken. [1] https://developer.arm.com/documentation/ddi0516/e/programmers-model/the-gic-500-register-map?lang=en [2] https://developer.arm.com/documentation/ihi0069/d [3] https://patchwork.kernel.org/project/linux-arm-kernel/patch/20180607233853.p7iw7nlxxuyi66og@kahuna/ [4] https://developer.arm.com/documentation/ddi0516/e/functional-description/operation/backwards-compatibility?lang=en -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel