From: Reiji Watanabe <reijiw@google.com>
To: Marc Zyngier <maz@kernel.org>, kvmarm@lists.cs.columbia.edu
Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
James Morse <james.morse@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Will Deacon <will@kernel.org>, Andrew Jones <drjones@redhat.com>,
Fuad Tabba <tabba@google.com>,
Peng Liang <liangpeng10@huawei.com>,
Peter Shier <pshier@google.com>,
Ricardo Koller <ricarkol@google.com>,
Oliver Upton <oupton@google.com>,
Jing Zhang <jingzhangos@google.com>,
Raghavendra Rao Anata <rananta@google.com>,
Reiji Watanabe <reijiw@google.com>
Subject: [PATCH v5 23/27] KVM: arm64: Trap disabled features of ID_AA64DFR0_EL1
Date: Sun, 13 Feb 2022 22:57:42 -0800 [thread overview]
Message-ID: <20220214065746.1230608-24-reijiw@google.com> (raw)
In-Reply-To: <20220214065746.1230608-1-reijiw@google.com>
Add feature_config_ctrl for PMUv3, PMS and TraceFilt, which are
indicated in ID_AA64DFR0_EL1, to program configuration registers
to trap guest's using those features when they are not exposed to
the guest.
Signed-off-by: Reiji Watanabe <reijiw@google.com>
---
arch/arm64/kvm/sys_regs.c | 64 +++++++++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index a3d22f7f642b..d91be297559d 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -349,6 +349,30 @@ static void feature_mte_trap_activate(struct kvm_vcpu *vcpu)
feature_trap_activate(vcpu, VCPU_HCR_EL2, HCR_TID5, HCR_DCT | HCR_ATA);
}
+static void feature_trace_trap_activate(struct kvm_vcpu *vcpu)
+{
+ if (has_vhe())
+ feature_trap_activate(vcpu, VCPU_CPTR_EL2, CPACR_EL1_TTA, 0);
+ else
+ feature_trap_activate(vcpu, VCPU_CPTR_EL2, CPTR_EL2_TTA, 0);
+}
+
+static void feature_pmuv3_trap_activate(struct kvm_vcpu *vcpu)
+{
+ feature_trap_activate(vcpu, VCPU_MDCR_EL2, MDCR_EL2_TPM, 0);
+}
+
+static void feature_pms_trap_activate(struct kvm_vcpu *vcpu)
+{
+ feature_trap_activate(vcpu, VCPU_MDCR_EL2, MDCR_EL2_TPMS,
+ MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT);
+}
+
+static void feature_tracefilt_trap_activate(struct kvm_vcpu *vcpu)
+{
+ feature_trap_activate(vcpu, VCPU_MDCR_EL2, MDCR_EL2_TTRF, 0);
+}
+
/* For ID_AA64PFR0_EL1 */
static struct feature_config_ctrl ftr_ctrl_ras = {
.ftr_reg = SYS_ID_AA64PFR0_EL1,
@@ -375,6 +399,39 @@ static struct feature_config_ctrl ftr_ctrl_mte = {
.trap_activate = feature_mte_trap_activate,
};
+/* For ID_AA64DFR0_EL1 */
+static struct feature_config_ctrl ftr_ctrl_trace = {
+ .ftr_reg = SYS_ID_AA64DFR0_EL1,
+ .ftr_shift = ID_AA64DFR0_TRACEVER_SHIFT,
+ .ftr_min = 1,
+ .ftr_signed = FTR_UNSIGNED,
+ .trap_activate = feature_trace_trap_activate,
+};
+
+static struct feature_config_ctrl ftr_ctrl_pmuv3 = {
+ .ftr_reg = SYS_ID_AA64DFR0_EL1,
+ .ftr_shift = ID_AA64DFR0_PMUVER_SHIFT,
+ .ftr_min = ID_AA64DFR0_PMUVER_8_0,
+ .ftr_signed = FTR_UNSIGNED,
+ .trap_activate = feature_pmuv3_trap_activate,
+};
+
+static struct feature_config_ctrl ftr_ctrl_pms = {
+ .ftr_reg = SYS_ID_AA64DFR0_EL1,
+ .ftr_shift = ID_AA64DFR0_PMSVER_SHIFT,
+ .ftr_min = ID_AA64DFR0_PMSVER_8_2,
+ .ftr_signed = FTR_UNSIGNED,
+ .trap_activate = feature_pms_trap_activate,
+};
+
+static struct feature_config_ctrl ftr_ctrl_tracefilt = {
+ .ftr_reg = SYS_ID_AA64DFR0_EL1,
+ .ftr_shift = ID_AA64DFR0_TRACE_FILT_SHIFT,
+ .ftr_min = 1,
+ .ftr_signed = FTR_UNSIGNED,
+ .trap_activate = feature_tracefilt_trap_activate,
+};
+
struct id_reg_info {
/* Register ID */
u32 sys_reg;
@@ -941,6 +998,13 @@ static struct id_reg_info id_aa64dfr0_el1_info = {
.init = init_id_aa64dfr0_el1_info,
.validate = validate_id_aa64dfr0_el1,
.vcpu_mask = vcpu_mask_id_aa64dfr0_el1,
+ .trap_features = &(const struct feature_config_ctrl *[]) {
+ &ftr_ctrl_trace,
+ &ftr_ctrl_pmuv3,
+ &ftr_ctrl_pms,
+ &ftr_ctrl_tracefilt,
+ NULL,
+ },
};
static struct id_reg_info id_dfr0_el1_info = {
--
2.35.1.265.g69c8d7142f-goog
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next prev parent reply other threads:[~2022-02-14 7:17 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-14 6:57 [PATCH v5 00/27] KVM: arm64: Make CPU ID registers writable by userspace Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 01/27] KVM: arm64: Introduce a validation function for an ID register Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 02/27] KVM: arm64: Save ID registers' sanitized value per guest Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 03/27] KVM: arm64: Introduce struct id_reg_info Reiji Watanabe
2022-02-17 5:14 ` Oliver Upton
2022-02-22 6:12 ` Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 04/27] KVM: arm64: Make ID_AA64PFR0_EL1 writable Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 05/27] KVM: arm64: Make ID_AA64PFR1_EL1 writable Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 06/27] KVM: arm64: Make ID_AA64ISAR0_EL1 writable Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 07/27] KVM: arm64: Make ID_AA64ISAR1_EL1 writable Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 08/27] KVM: arm64: Make ID_AA64MMFR0_EL1 writable Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 09/27] KVM: arm64: Make ID_AA64MMFR1_EL1 writable Reiji Watanabe
2022-02-15 18:53 ` Oliver Upton
2022-02-15 20:24 ` Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 10/27] KVM: arm64: Hide IMPLEMENTATION DEFINED PMU support for the guest Reiji Watanabe
2022-02-15 18:57 ` Oliver Upton
2022-02-16 2:52 ` Reiji Watanabe
2022-02-17 4:59 ` Oliver Upton
2022-02-14 6:57 ` [PATCH v5 11/27] KVM: arm64: Make ID_AA64DFR0_EL1 writable Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 12/27] KVM: arm64: Make ID_DFR0_EL1 writable Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 13/27] KVM: arm64: Make MVFR1_EL1 writable Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 14/27] KVM: arm64: Make ID registers without id_reg_info writable Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 15/27] KVM: arm64: Add consistency checking for frac fields of ID registers Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 16/27] KVM: arm64: Introduce KVM_CAP_ARM_ID_REG_CONFIGURABLE capability Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 17/27] KVM: arm64: Add kunit test for ID register validation Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 18/27] KVM: arm64: Use vcpu->arch cptr_el2 to track value of cptr_el2 for VHE Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 19/27] KVM: arm64: Use vcpu->arch.mdcr_el2 to track value of mdcr_el2 Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 20/27] KVM: arm64: Introduce framework to trap disabled features Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 21/27] KVM: arm64: Trap disabled features of ID_AA64PFR0_EL1 Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 22/27] KVM: arm64: Trap disabled features of ID_AA64PFR1_EL1 Reiji Watanabe
2022-02-14 6:57 ` Reiji Watanabe [this message]
2022-02-14 6:57 ` [PATCH v5 24/27] KVM: arm64: Trap disabled features of ID_AA64MMFR1_EL1 Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 25/27] KVM: arm64: Trap disabled features of ID_AA64ISAR1_EL1 Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 26/27] KVM: arm64: Add kunit test for trap initialization Reiji Watanabe
2022-02-14 6:57 ` [PATCH v5 27/27] KVM: arm64: selftests: Introduce id_reg_test Reiji Watanabe
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