From: Billy Tsai <billy_tsai@aspeedtech.com>
To: <jic23@kernel.org>, <lars@metafoo.de>, <joel@jms.id.au>,
<andrew@aj.id.au>, <billy_tsai@aspeedtech.com>,
<colin.king@canonical.com>, <linux-iio@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-aspeed@lists.ozlabs.org>, <linux-kernel@vger.kernel.org>
Cc: Konstantin Klubnichkin <kitsok@yandex-team.ru>
Subject: [PATCH] iio: adc: aspeed: Add divider flag to fix incorrect voltage reading.
Date: Fri, 18 Feb 2022 16:57:08 +0800 [thread overview]
Message-ID: <20220218085708.8194-1-billy_tsai@aspeedtech.com> (raw)
The formula for the ADC sampling period in ast2400/ast2500 is:
ADC clock period = PCLK * 2 * (ADC0C[31:17] + 1) * (ADC0C[9:0])
When ADC0C[9:0] is set to 0 the sampling voltage will be lower than
expected, because the hardware may not have enough time to
charge/discharge to a stable voltage.
Reported-by: Konstantin Klubnichkin <kitsok@yandex-team.ru>
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
---
drivers/iio/adc/aspeed_adc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c
index a957cad1bfab..ffae64f39221 100644
--- a/drivers/iio/adc/aspeed_adc.c
+++ b/drivers/iio/adc/aspeed_adc.c
@@ -539,7 +539,9 @@ static int aspeed_adc_probe(struct platform_device *pdev)
data->clk_scaler = devm_clk_hw_register_divider(
&pdev->dev, clk_name, clk_parent_name, scaler_flags,
data->base + ASPEED_REG_CLOCK_CONTROL, 0,
- data->model_data->scaler_bit_width, 0, &data->clk_lock);
+ data->model_data->scaler_bit_width,
+ data->model_data->need_prescaler ? CLK_DIVIDER_ONE_BASED : 0,
+ &data->clk_lock);
if (IS_ERR(data->clk_scaler))
return PTR_ERR(data->clk_scaler);
--
2.25.1
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next reply other threads:[~2022-02-18 8:58 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-18 8:57 Billy Tsai [this message]
2022-02-19 16:00 ` [PATCH] iio: adc: aspeed: Add divider flag to fix incorrect voltage reading Jonathan Cameron
2022-02-21 0:47 ` Billy Tsai
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