From: Teresa Remmet <t.remmet@phytec.de>
To: linux-arm-kernel@lists.infradead.org
Cc: Heiko Schocher <hs@denx.de>,
Jonas Kuenstler <j.kuenstler@phytec.de>,
Haibo Chen <haibo.chen@nxp.com>,
NXP Linux Team <linux-imx@nxp.com>,
Fabio Estevam <festevam@gmail.com>,
Sascha Hauer <s.hauer@pengutronix.de>,
Shawn Guo <shawnguo@kernel.org>, Rob Herring <robh+dt@kernel.org>
Subject: [PATCH v2 2/7] arm64: dts: imx8mp-phycore-som: Adapt eMMC drive strength
Date: Fri, 18 Feb 2022 13:04:53 +0100 [thread overview]
Message-ID: <20220218120458.14036-3-t.remmet@phytec.de> (raw)
In-Reply-To: <20220218120458.14036-1-t.remmet@phytec.de>
Set eMMC drive strength for USDHC3_DATA lines (200Mhz)
to X4 for signal improvement.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
---
Changes in v2:
- Added Reviewed-by tag
.../boot/dts/freescale/imx8mp-phycore-som.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
index 778f601a0119..927290990d02 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
@@ -299,14 +299,14 @@ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>;
};
--
2.25.1
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next prev parent reply other threads:[~2022-02-18 12:58 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-18 12:04 [PATCH v2 0/7] arm64: dts: phyCORE-i.MX8MP SoM updates Teresa Remmet
2022-02-18 12:04 ` [PATCH v2 1/7] arm64: dts: imx8mp-phycore-som: Set minimum output impedance for eth phy Teresa Remmet
2022-02-18 12:04 ` Teresa Remmet [this message]
2022-02-18 12:04 ` [PATCH v2 3/7] arm64: dts: imx8mp-phycore-som: Reduce drive strength for fec tx lines Teresa Remmet
2022-02-18 12:04 ` [PATCH v2 4/7] arm64: dts: imx8mp-phycore-som: Update WDOG muxing Teresa Remmet
2022-02-18 12:04 ` [PATCH v2 5/7] arm64: dts: imx8mp-phycore-som: Set VDD_ARM run and standby voltage Teresa Remmet
2022-02-18 12:04 ` [PATCH v2 6/7] arm64: dts: imx8mp-phycore-som: LDO5 needs to be enabled instead of LDO4 Teresa Remmet
2022-02-18 12:04 ` [PATCH v2 7/7] arm64: dts: imx8mp-phycore-som: Set usdhc root clock for eMMC Teresa Remmet
2022-02-21 6:11 ` [PATCH v2 0/7] arm64: dts: phyCORE-i.MX8MP SoM updates Shawn Guo
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