From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4A429C433F5 for ; Fri, 25 Feb 2022 00:03:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Message-ID: Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:References: List-Owner; bh=iFJ/c3NZgX+6ScPusIis7+FnBArh0bTGTTGEXmrzikw=; b=4fxqPRsFu8HtMX ELfEIue1chgidoJtaqJb6lFcUa5D/mjFaj0eTRv4Rch5YlDDkHDBfr8sT0FLT6rVeBkjRKcYeBmi+ 8/Gd3D3WnYeLxgD5JawtGmyHX/GaCmlSm2HLfGh+EeIhGuCsi26ySDHrsWNADzCT5EPGElrM/PMni sijHW8sd7eShFnwb/2ZhwaB2iv5lRxpFg18nZpJ9XB1XweQNoA3VJ4Gkj6gExHF5pkTQ2S2rwRnUj 9JjNIC0ZCCRucJ8NEys0ZL+ORQEbnZNXv8oDo8jGNev9ROQu18g8Kfv8oD0gzBfKywdbGtuBWf5af n70GNVK+5cssMvwIY10g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nNO48-002kgL-Ra; Fri, 25 Feb 2022 00:02:33 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nNO45-002kfj-9w for linux-arm-kernel@lists.infradead.org; Fri, 25 Feb 2022 00:02:30 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C6A9F61CCA; Fri, 25 Feb 2022 00:02:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EEC0FC340E9; Fri, 25 Feb 2022 00:02:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645747348; bh=B5C/irAy5Ksddk0oeAfWCNVXMjjzHhykOfXsUHlDfiU=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=FnBk0yBT8P4/HNhq/XNKvxXaoDFhHO5SqZmvwFrWWsqUJQw/kezs9NKd44trxe2ol dAD/Lef2N0wukNLou1M1AorFCxCh1Ck+CeuJyDXugG0qE4EMC/GNA98cpRN9PWi2Tu xNphdc525yVvjRdNZVda4zNu4ZpZg7osW6myVg1OjCalqiQI3nvgn3ScInTdNp2iJu ze0uT9v8Ux3rbKeCrE7WiwNDbuA4Hi5HksoggPw3TYjsU0SM4Pr9dpAMoqJ0VYipVM 4u/FLsn2RhgLPO8FTk3ZV4fXrwxRMLeoNmv2/V/k969Z8FiCv3TU4U9P/T09VOSZGo k6mQtILoRoVnQ== Date: Thu, 24 Feb 2022 18:02:26 -0600 From: Bjorn Helgaas To: Pali =?iso-8859-1?Q?Roh=E1r?= Cc: Lorenzo Pieralisi , Bjorn Helgaas , Rob Herring , Thomas Petazzoni , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Marek =?iso-8859-1?Q?Beh=FAn?= , Russell King , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v4 04/12] dt-bindings: PCI: mvebu: Add num-lanes property Message-ID: <20220225000226.GA304258@bhelgaas> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220222155030.988-5-pali@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220224_160229_413383_F690FFE0 X-CRM114-Status: GOOD ( 21.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Feb 22, 2022 at 04:50:22PM +0100, Pali Roh=E1r wrote: > Controller driver needs to correctly configure PCIe link if it contains 1 > or 4 SerDes PCIe lanes. Therefore add a new 'num-lanes' DT property for > mvebu PCIe controller. Property 'num-lanes' seems to be de-facto standard > way how number of lanes is specified in other PCIe controllers. > = > Signed-off-by: Pali Roh=E1r > Acked-by: Rob Herring > --- > Documentation/devicetree/bindings/pci/mvebu-pci.txt | 11 +++++++++++ > 1 file changed, 11 insertions(+) > = > diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Docume= ntation/devicetree/bindings/pci/mvebu-pci.txt > index 6173af6885f8..24225852bce0 100644 > --- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt > +++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt > @@ -77,6 +77,7 @@ and the following optional properties: > - marvell,pcie-lane: the physical PCIe lane number, for ports having > multiple lanes. If this property is not found, we assume that the > value is 0. > +- num-lanes: number of SerDes PCIe lanes for this link (1 or 4) > - reset-gpios: optional GPIO to PERST# > - reset-delay-us: delay in us to wait after reset de-assertion, if not > specified will default to 100ms, as required by the PCIe specification. > @@ -141,6 +142,7 @@ pcie-controller { > interrupt-map =3D <0 0 0 0 &mpic 58>; > marvell,pcie-port =3D <0>; > marvell,pcie-lane =3D <0>; > + num-lanes =3D <1>; Is this patch really necessary? AFAICS, the related driver change only sets "port->is_x4 =3D true" when "num-lanes =3D <4>", and in all other cases it defaults to a Max Link Width of 1: lnkcap |=3D (port->is_x4 ? 4 : 1) << 4; I don't see the point of adding a value that we don't validate or do anything with. E.g., I don't see an error message that would catch "num-lanes =3D <3>". Bjorn _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel