From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C86B1C433EF for ; Fri, 4 Mar 2022 17:23:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2qyF1h/ZW7Y7A65XYrWlESvMCnBnP7kflpahDKyjJ8k=; b=RMCYRnt9LJNhIl 58ss3K2KkBBdtfMa1/RoafyBHkfEOGc2eO+wqTOACCUZ14deL5K4relVodNeB1j63PWmTvQ1fdJcC kpliaFXstt4Een0V+m0259LHN0pinagtSMRu0pIGDSsoxTIziDRa2Lf0snaBM8KOi+mAkFs8Qycr2 xmkBLlYnWbBhzoXhWsgEBglt0eWsZJ1GgbhuGCtX/HCPLEG1CIa8hhvIhRYqtumULn54oCU+NXr0m VmQpC/s5mONGXDNL+LfhHnBwzbNnUc4jG4fcB8CeIKvtsqBO0AP4CuQE4WNj1OappQZVKSSrgjxc+ oj/LdlKCJYzh2R74Gjhw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQBcn-00BGxb-FQ; Fri, 04 Mar 2022 17:21:53 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nQBah-00BFbd-Lm for linux-arm-kernel@lists.infradead.org; Fri, 04 Mar 2022 17:19:45 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1F57A1424; Fri, 4 Mar 2022 09:19:43 -0800 (PST) Received: from e121896.arm.com (unknown [10.57.42.166]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7CCAA3F73D; Fri, 4 Mar 2022 09:19:41 -0800 (PST) From: James Clark To: suzuki.poulose@arm.com, coresight@lists.linaro.org, mike.leach@linaro.org, anshuman.khandual@arm.com Cc: mathieu.poirier@linaro.org, leo.yan@linaro.com, James Clark , Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 08/15] coresight: etm4x: Cleanup TRCSTALLCTLR register accesses Date: Fri, 4 Mar 2022 17:19:05 +0000 Message-Id: <20220304171913.2292458-9-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220304171913.2292458-1-james.clark@arm.com> References: <20220304171913.2292458-1-james.clark@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220304_091943_805207_C5B12A18 X-CRM114-Status: UNSURE ( 9.85 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This is a no-op change for style and consistency and has no effect on the binary output by the compiler. In sysreg.h fields are defined as the register name followed by the field name and then _MASK. This allows for grepping for fields by name rather than using magic numbers. Signed-off-by: James Clark --- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 12 ++++++------ drivers/hwtracing/coresight/coresight-etm4x.h | 4 ++++ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 2d29e9daf515..cd24590ea38a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -397,22 +397,22 @@ static ssize_t mode_store(struct device *dev, /* bit[8], Instruction stall bit */ if ((config->mode & ETM_MODE_ISTALL_EN) && (drvdata->stallctl == true)) - config->stall_ctrl |= BIT(8); + config->stall_ctrl |= TRCSTALLCTLR_ISTALL; else - config->stall_ctrl &= ~BIT(8); + config->stall_ctrl &= ~TRCSTALLCTLR_ISTALL; /* bit[10], Prioritize instruction trace bit */ if (config->mode & ETM_MODE_INSTPRIO) - config->stall_ctrl |= BIT(10); + config->stall_ctrl |= TRCSTALLCTLR_INSTPRIORITY; else - config->stall_ctrl &= ~BIT(10); + config->stall_ctrl &= ~TRCSTALLCTLR_INSTPRIORITY; /* bit[13], Trace overflow prevention bit */ if ((config->mode & ETM_MODE_NOOVERFLOW) && (drvdata->nooverflow == true)) - config->stall_ctrl |= BIT(13); + config->stall_ctrl |= TRCSTALLCTLR_NOOVERFLOW; else - config->stall_ctrl &= ~BIT(13); + config->stall_ctrl &= ~TRCSTALLCTLR_NOOVERFLOW; /* bit[9] Start/stop logic control bit */ if (config->mode & ETM_MODE_VIEWINST_STARTSTOP) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index cbba46f14ada..36934056a5dc 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -196,6 +196,10 @@ #define TRCEVENTCTL1R_ATB BIT(11) #define TRCEVENTCTL1R_LPOVERRIDE BIT(12) +#define TRCSTALLCTLR_ISTALL BIT(8) +#define TRCSTALLCTLR_INSTPRIORITY BIT(10) +#define TRCSTALLCTLR_NOOVERFLOW BIT(13) + /* * System instructions to access ETM registers. * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions -- 2.28.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel