From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 99BB5C433EF for ; Sat, 12 Mar 2022 12:06:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=jzEgElfazRSKiRbIpuH/LSRp5GG92KDtzp6p//YVx4U=; b=AYUUIG/ekp7qOC HcKSZpNxL0kD3/bEONd0y1gErn/K/yWx85+Q/wZKhhBXOfrAqWsuvBiGGgdEkP7Sxkn205X5vnMGG oPw1FvbSViTfdaJPliqjvAyULWu8lVLVCYt6Vw/a9M9I2l5gQlcvKcG2mVoQFCJyK2LXiX+veM4km nsvBWPIxvowig5Jwi02gaB3FwAh6ADcx/vjhYv0oaZIqOW8x2EnTjIYDLUsz5+6RgU5lx4jenTe7T TR9lI+5fd4BD6qwLZCw1k4y8muIrLapjg9e7j6z+6zAXdGxitC96cR5OoxvWk0kS2qJpHtfscLqME nMuuuTodbLMCB2AEn1aQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nT0Uy-001G11-Dy; Sat, 12 Mar 2022 12:05:29 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nT0Uw-001G0O-7E for linux-arm-kernel@bombadil.infradead.org; Sat, 12 Mar 2022 12:05:26 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=ejU6WI5jmR2smgFVL5pnl7wQ3KUvcvihCK5Q5wkohU0=; b=MMV8ty8liqf04/w5STtdINZm4Y qFQph5LR3+2BXUbw+lafq+o8K1yT1atlLjBFF/jmWnu1XVXeRrSjKprw0FG0g06vQpVGVHT4D9fEn FfOSHDKLdNYuk3YdX46TAAIgnHfIGWUejhLCILMpp3FCElLuZMfaSMdWPiaAgeBTWxtg+mKwaNn8W DvDBT9luafIUSMqE2+MUgyv7b4x4rBBiqHEgKUPiOEQJv7jJqCQNfjokF2MBLvxWulkmvKO+U6qAw kgYaYVrQ4MWZ+XVl27qQqizeX8uShACA7ppUccX+8HV7g4d/OuBGIMfII+3iSlJ+83eyynXhjJIaO T730WJvA==; Received: from j217100.upc-j.chello.nl ([24.132.217.100] helo=worktop.programming.kicks-ass.net) by desiato.infradead.org with esmtpsa (Exim 4.94.2 #2 (Red Hat Linux)) id 1nT0Up-000A3C-Uo; Sat, 12 Mar 2022 12:05:20 +0000 Received: by worktop.programming.kicks-ass.net (Postfix, from userid 1000) id 5C28598791D; Sat, 12 Mar 2022 13:05:18 +0100 (CET) Date: Sat, 12 Mar 2022 13:05:18 +0100 From: Peter Zijlstra To: Qing Wang Cc: Catalin Marinas , Will Deacon , Sudeep Holla , Greg Kroah-Hartman , "Rafael J. Wysocki" , Ingo Molnar , Juri Lelli , Vincent Guittot , Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Daniel Bristot de Oliveira , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH V2] sched: topology: make cache topology separate from cpu topology Message-ID: <20220312120518.GC6235@worktop.programming.kicks-ass.net> References: <1646969135-26647-1-git-send-email-wangqing@vivo.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1646969135-26647-1-git-send-email-wangqing@vivo.com> X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Mar 10, 2022 at 07:25:33PM -0800, Qing Wang wrote: > From: Wang Qing > > Some architectures(e.g. ARM64), caches are implemented like below: > SD(Level 1): ************ DIE ************ > SD(Level 0): **** MC **** **** MC ***** > cluster: **cluster 0** **cluster 1** > cores: 0 1 2 3 4 5 6 7 > cache(Level 1): C C C C C C C C > cache(Level 2): **C** **C** **C** **C** > cache(Level 3): *******shared Level 3******** > sd_llc_id(current): 0 0 0 0 4 4 4 4 > sd_llc_id(should be): 0 0 2 2 4 4 6 6 > > Caches and cpus have different topology, this causes cpus_share_cache() > return the wrong value in sd, which will affect the CPU load balance. Then fix your SD_flags already. > diff --git a/include/linux/arch_topology.h b/include/linux/arch_topology.h > index cce6136b..3048fa6 > --- a/include/linux/arch_topology.h > +++ b/include/linux/arch_topology.h > @@ -82,6 +82,8 @@ extern struct cpu_topology cpu_topology[NR_CPUS]; > #define topology_cluster_cpumask(cpu) (&cpu_topology[cpu].cluster_sibling) > #define topology_llc_cpumask(cpu) (&cpu_topology[cpu].llc_sibling) > void init_cpu_topology(void); > +void init_cpu_cache_topology(void); > +void fix_cpu_llc(int cpu, int *first_cpu, int *cpu_num); > void store_cpu_topology(unsigned int cpuid); > const struct cpumask *cpu_coregroup_mask(int cpu); > const struct cpumask *cpu_clustergroup_mask(int cpu); > diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c > index d201a70..d894ced > --- a/kernel/sched/topology.c > +++ b/kernel/sched/topology.c > @@ -661,6 +661,9 @@ static void update_top_cache_domain(int cpu) > if (sd) { > id = cpumask_first(sched_domain_span(sd)); > size = cpumask_weight(sched_domain_span(sd)); > +#ifdef CONFIG_GENERIC_ARCH_TOPOLOGY > + fix_cpu_llc(cpu, &id, &size); > +#endif > sds = sd->shared; > } NAK on that. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel