From: Jiaxin Yu <jiaxin.yu@mediatek.com>
To: <broonie@kernel.org>, <robh+dt@kernel.org>,
<angelogioacchino.delregno@collabora.com>
Cc: <aaronyu@google.com>, <matthias.bgg@gmail.com>,
<trevor.wu@mediatek.com>, <tzungbi@google.com>,
<julianbraha@gmail.com>, <alsa-devel@alsa-project.org>,
<devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
Jiaxin Yu <jiaxin.yu@mediatek.com>
Subject: [v3 12/19] ASoC: mediatek: mt8186: support gpio control in platform driver
Date: Sun, 13 Mar 2022 23:10:16 +0800 [thread overview]
Message-ID: <20220313151023.21229-13-jiaxin.yu@mediatek.com> (raw)
In-Reply-To: <20220313151023.21229-1-jiaxin.yu@mediatek.com>
Add gpio control for all audio interface separately.
Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
---
sound/soc/mediatek/mt8186/mt8186-afe-gpio.c | 244 ++++++++++++++++++++
sound/soc/mediatek/mt8186/mt8186-afe-gpio.h | 19 ++
2 files changed, 263 insertions(+)
create mode 100644 sound/soc/mediatek/mt8186/mt8186-afe-gpio.c
create mode 100644 sound/soc/mediatek/mt8186/mt8186-afe-gpio.h
diff --git a/sound/soc/mediatek/mt8186/mt8186-afe-gpio.c b/sound/soc/mediatek/mt8186/mt8186-afe-gpio.c
new file mode 100644
index 000000000000..5ba28095b7da
--- /dev/null
+++ b/sound/soc/mediatek/mt8186/mt8186-afe-gpio.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// mt8186-afe-gpio.c -- Mediatek 8186 afe gpio ctrl
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
+
+#include <linux/gpio.h>
+#include <linux/pinctrl/consumer.h>
+
+#include "mt8186-afe-common.h"
+#include "mt8186-afe-gpio.h"
+
+struct pinctrl *aud_pinctrl;
+
+enum mt8186_afe_gpio {
+ MT8186_AFE_GPIO_CLK_MOSI_OFF,
+ MT8186_AFE_GPIO_CLK_MOSI_ON,
+ MT8186_AFE_GPIO_CLK_MISO_OFF,
+ MT8186_AFE_GPIO_CLK_MISO_ON,
+ MT8186_AFE_GPIO_DAT_MISO_OFF,
+ MT8186_AFE_GPIO_DAT_MISO_ON,
+ MT8186_AFE_GPIO_DAT_MOSI_OFF,
+ MT8186_AFE_GPIO_DAT_MOSI_ON,
+ MT8186_AFE_GPIO_I2S0_OFF,
+ MT8186_AFE_GPIO_I2S0_ON,
+ MT8186_AFE_GPIO_I2S1_OFF,
+ MT8186_AFE_GPIO_I2S1_ON,
+ MT8186_AFE_GPIO_I2S2_OFF,
+ MT8186_AFE_GPIO_I2S2_ON,
+ MT8186_AFE_GPIO_I2S3_OFF,
+ MT8186_AFE_GPIO_I2S3_ON,
+ MT8186_AFE_GPIO_TDM_OFF,
+ MT8186_AFE_GPIO_TDM_ON,
+ MT8186_AFE_GPIO_PCM_OFF,
+ MT8186_AFE_GPIO_PCM_ON,
+ MT8186_AFE_GPIO_GPIO_NUM
+};
+
+struct audio_gpio_attr {
+ const char *name;
+ bool gpio_prepare;
+ struct pinctrl_state *gpioctrl;
+};
+
+static struct audio_gpio_attr aud_gpios[MT8186_AFE_GPIO_GPIO_NUM] = {
+ [MT8186_AFE_GPIO_CLK_MOSI_OFF] = {"aud_clk_mosi_off", false, NULL},
+ [MT8186_AFE_GPIO_CLK_MOSI_ON] = {"aud_clk_mosi_on", false, NULL},
+ [MT8186_AFE_GPIO_CLK_MISO_OFF] = {"aud_clk_miso_off", false, NULL},
+ [MT8186_AFE_GPIO_CLK_MISO_ON] = {"aud_clk_miso_on", false, NULL},
+ [MT8186_AFE_GPIO_DAT_MISO_OFF] = {"aud_dat_miso_off", false, NULL},
+ [MT8186_AFE_GPIO_DAT_MISO_ON] = {"aud_dat_miso_on", false, NULL},
+ [MT8186_AFE_GPIO_DAT_MOSI_OFF] = {"aud_dat_mosi_off", false, NULL},
+ [MT8186_AFE_GPIO_DAT_MOSI_ON] = {"aud_dat_mosi_on", false, NULL},
+ [MT8186_AFE_GPIO_I2S0_OFF] = {"aud_gpio_i2s0_off", false, NULL},
+ [MT8186_AFE_GPIO_I2S0_ON] = {"aud_gpio_i2s0_on", false, NULL},
+ [MT8186_AFE_GPIO_I2S1_OFF] = {"aud_gpio_i2s1_off", false, NULL},
+ [MT8186_AFE_GPIO_I2S1_ON] = {"aud_gpio_i2s1_on", false, NULL},
+ [MT8186_AFE_GPIO_I2S2_OFF] = {"aud_gpio_i2s2_off", false, NULL},
+ [MT8186_AFE_GPIO_I2S2_ON] = {"aud_gpio_i2s2_on", false, NULL},
+ [MT8186_AFE_GPIO_I2S3_OFF] = {"aud_gpio_i2s3_off", false, NULL},
+ [MT8186_AFE_GPIO_I2S3_ON] = {"aud_gpio_i2s3_on", false, NULL},
+ [MT8186_AFE_GPIO_TDM_OFF] = {"aud_gpio_tdm_off", false, NULL},
+ [MT8186_AFE_GPIO_TDM_ON] = {"aud_gpio_tdm_on", false, NULL},
+ [MT8186_AFE_GPIO_PCM_OFF] = {"aud_gpio_pcm_off", false, NULL},
+ [MT8186_AFE_GPIO_PCM_ON] = {"aud_gpio_pcm_on", false, NULL},
+};
+
+static DEFINE_MUTEX(gpio_request_mutex);
+
+int mt8186_afe_gpio_init(struct device *dev)
+{
+ int i, j, ret;
+
+ aud_pinctrl = devm_pinctrl_get(dev);
+ if (IS_ERR(aud_pinctrl)) {
+ ret = PTR_ERR(aud_pinctrl);
+ dev_err(dev, "%s(), ret %d, cannot get aud_pinctrl!\n",
+ __func__, ret);
+ return ret;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(aud_gpios); i++) {
+ aud_gpios[i].gpioctrl = pinctrl_lookup_state(aud_pinctrl,
+ aud_gpios[i].name);
+ if (IS_ERR(aud_gpios[i].gpioctrl)) {
+ ret = PTR_ERR(aud_gpios[i].gpioctrl);
+ dev_info(dev, "%s(), pinctrl_lookup_state %s fail, ret %d\n",
+ __func__, aud_gpios[i].name, ret);
+ } else {
+ aud_gpios[i].gpio_prepare = true;
+ }
+ }
+
+ /* gpio status init */
+ for (i = MT8186_DAI_ADDA; i <= MT8186_DAI_TDM_IN; i++) {
+ for (j = 0; j <= 1; j++)
+ mt8186_afe_gpio_request(dev, false, i, j);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mt8186_afe_gpio_init);
+
+static int mt8186_afe_gpio_select(struct device *dev,
+ enum mt8186_afe_gpio type)
+{
+ int ret = 0;
+
+ if (type < 0 || type >= MT8186_AFE_GPIO_GPIO_NUM) {
+ dev_err(dev, "%s(), error, invalid gpio type %d\n",
+ __func__, type);
+ return -EINVAL;
+ }
+
+ if (!aud_gpios[type].gpio_prepare) {
+ dev_err(dev, "%s(), error, gpio type %d not prepared\n",
+ __func__, type);
+ return -EIO;
+ }
+
+ ret = pinctrl_select_state(aud_pinctrl,
+ aud_gpios[type].gpioctrl);
+ if (ret) {
+ dev_err(dev, "%s(), error, can not set gpio type %d\n",
+ __func__, type);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mt8186_afe_gpio_adda_dl(struct device *dev, bool enable)
+{
+ int ret;
+
+ if (enable) {
+ ret = mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_CLK_MOSI_ON);
+ if (ret) {
+ dev_err(dev, "%s(), MOSI CLK ON slect fail!\n", __func__);
+ return ret;
+ }
+
+ ret = mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_DAT_MOSI_ON);
+ if (ret) {
+ dev_err(dev, "%s(), MOSI DAT ON slect fail!\n", __func__);
+ return ret;
+ }
+ } else {
+ ret = mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_DAT_MOSI_OFF);
+ if (ret) {
+ dev_err(dev, "%s(), MOSI DAT OFF slect fail!\n", __func__);
+ return ret;
+ }
+
+ ret = mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_CLK_MOSI_OFF);
+ if (ret) {
+ dev_err(dev, "%s(), MOSI CLK ON slect fail!\n", __func__);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int mt8186_afe_gpio_adda_ul(struct device *dev, bool enable)
+{
+ int ret;
+
+ if (enable) {
+ ret = mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_CLK_MISO_ON);
+ if (ret) {
+ dev_err(dev, "%s(), MISO CLK ON slect fail!\n", __func__);
+ return ret;
+ }
+
+ ret = mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_DAT_MISO_ON);
+ if (ret) {
+ dev_err(dev, "%s(), MISO DAT ON slect fail!\n", __func__);
+ return ret;
+ }
+ } else {
+ ret = mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_DAT_MISO_OFF);
+ if (ret) {
+ dev_err(dev, "%s(), MISO DAT OFF slect fail!\n", __func__);
+ return ret;
+ }
+
+ ret = mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_CLK_MISO_OFF);
+ if (ret) {
+ dev_err(dev, "%s(), MISO CLK OFF slect fail!\n", __func__);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+int mt8186_afe_gpio_request(struct device *dev, bool enable,
+ int dai, int uplink)
+{
+ enum mt8186_afe_gpio sel;
+ int ret = -EINVAL;
+
+ mutex_lock(&gpio_request_mutex);
+
+ switch (dai) {
+ case MT8186_DAI_ADDA:
+ if (uplink)
+ ret = mt8186_afe_gpio_adda_ul(dev, enable);
+ else
+ ret = mt8186_afe_gpio_adda_dl(dev, enable);
+ goto unlock;
+ case MT8186_DAI_I2S_0:
+ sel = enable ? MT8186_AFE_GPIO_I2S0_ON : MT8186_AFE_GPIO_I2S0_OFF;
+ break;
+ case MT8186_DAI_I2S_1:
+ sel = enable ? MT8186_AFE_GPIO_I2S1_ON : MT8186_AFE_GPIO_I2S1_OFF;
+ break;
+ case MT8186_DAI_I2S_2:
+ sel = enable ? MT8186_AFE_GPIO_I2S2_ON : MT8186_AFE_GPIO_I2S2_OFF;
+ break;
+ case MT8186_DAI_I2S_3:
+ sel = enable ? MT8186_AFE_GPIO_I2S3_ON : MT8186_AFE_GPIO_I2S3_OFF;
+ break;
+ case MT8186_DAI_TDM_IN:
+ sel = enable ? MT8186_AFE_GPIO_TDM_ON : MT8186_AFE_GPIO_TDM_OFF;
+ break;
+ case MT8186_DAI_PCM:
+ sel = enable ? MT8186_AFE_GPIO_PCM_ON : MT8186_AFE_GPIO_PCM_OFF;
+ break;
+ default:
+ mutex_unlock(&gpio_request_mutex);
+ dev_err(dev, "%s(), invalid dai %d\n", __func__, dai);
+ goto unlock;
+ }
+
+ ret = mt8186_afe_gpio_select(dev, sel);
+
+unlock:
+ mutex_unlock(&gpio_request_mutex);
+
+ return ret;
+}
diff --git a/sound/soc/mediatek/mt8186/mt8186-afe-gpio.h b/sound/soc/mediatek/mt8186/mt8186-afe-gpio.h
new file mode 100644
index 000000000000..1ddc27838eb1
--- /dev/null
+++ b/sound/soc/mediatek/mt8186/mt8186-afe-gpio.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * mt6833-afe-gpio.h -- Mediatek 6833 afe gpio ctrl definition
+ *
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
+ */
+
+#ifndef _MT8186_AFE_GPIO_H_
+#define _MT8186_AFE_GPIO_H_
+
+struct mtk_base_afe;
+
+int mt8186_afe_gpio_init(struct device *dev);
+
+int mt8186_afe_gpio_request(struct device *dev, bool enable,
+ int dai, int uplink);
+
+#endif
--
2.18.0
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next prev parent reply other threads:[~2022-03-13 15:14 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-13 15:10 [v3 00/19] ASoC: mediatek: Add support for MT8186 SoC Jiaxin Yu
2022-03-13 15:10 ` [v3 01/19] ASoC: mediatek: mt6366: support for mt6366 codec Jiaxin Yu
2022-03-13 15:10 ` [v3 02/19] dt-bindings: mediatek: mt6358: add new compatible for using mt6366 Jiaxin Yu
2022-03-23 17:09 ` Rob Herring
2022-03-13 15:10 ` [v3 03/19] ASoC: mediatek: mt8186: support audsys clock control Jiaxin Yu
2022-03-14 10:18 ` AngeloGioacchino Del Regno
2022-03-13 15:10 ` [v3 04/19] ASoC: mediatek: mt8186: support adda in platform driver Jiaxin Yu
2022-03-14 10:25 ` AngeloGioacchino Del Regno
2022-03-13 15:10 ` [v3 05/19] ASoC: mediatek: mt8186: support hostless " Jiaxin Yu
2022-03-14 10:25 ` AngeloGioacchino Del Regno
2022-03-13 15:10 ` [v3 06/19] ASoC: mediatek: mt8186: support hw gain " Jiaxin Yu
2022-03-14 10:25 ` AngeloGioacchino Del Regno
2022-03-13 15:10 ` [v3 07/19] ASoC: mediatek: mt8186: support i2s " Jiaxin Yu
2022-03-14 10:28 ` AngeloGioacchino Del Regno
2022-03-13 15:10 ` [v3 08/19] ASoC: mediatek: mt8186: support pcm " Jiaxin Yu
2022-03-14 10:29 ` AngeloGioacchino Del Regno
2022-03-13 15:10 ` [v3 09/19] ASoC: mediatek: mt8186: support src " Jiaxin Yu
2022-03-14 10:34 ` AngeloGioacchino Del Regno
2022-03-13 15:10 ` [v3 10/19] ASoC: mediatek: mt8186: support tdm " Jiaxin Yu
2022-03-14 10:39 ` AngeloGioacchino Del Regno
2022-03-15 13:15 ` Mark Brown
2022-03-15 13:19 ` AngeloGioacchino Del Regno
2022-03-13 15:10 ` [v3 11/19] ASoC: mediatek: mt8186: support audio clock control " Jiaxin Yu
2022-03-13 15:10 ` Jiaxin Yu [this message]
2022-03-13 15:10 ` [v3 14/19] dt-bindings: mediatek: mt8186: add audio afe document Jiaxin Yu
2022-03-14 10:25 ` AngeloGioacchino Del Regno
2022-03-13 15:10 ` [v3 15/19] ASoC: mediatek: mt8186: add machine driver with mt6366, da7219 and max98357 Jiaxin Yu
2022-03-14 10:44 ` AngeloGioacchino Del Regno
2022-04-05 4:06 ` Jiaxin Yu
2022-03-13 15:10 ` [v3 16/19] dt-bindings: mediatek: mt8186: add mt8186-mt6366-da7219-max98357 document Jiaxin Yu
2022-03-13 15:10 ` [v3 17/19] ASoC: mediatek: mt8186: add machine driver with mt6366, rt1019 and rt5682s Jiaxin Yu
2022-03-13 15:10 ` [v3 18/19] dt-bindings: mediatek: mt8186: add mt8186-mt6366-rt1019-rt5682s document Jiaxin Yu
2022-03-13 15:10 ` [v3 19/19] ASoC: mediatek: mt6358: add missing EXPORT_SYMBOLs Jiaxin Yu
2022-03-14 10:18 ` AngeloGioacchino Del Regno
2022-03-14 11:55 ` Jiaxin Yu
2022-04-05 3:04 ` Jiaxin Yu
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