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Wed, 16 Mar 2022 05:42:15 -0700 (PDT) Date: Wed, 16 Mar 2022 20:42:08 +0800 From: Leo Yan To: German Gomez Cc: Ali Saidi , acme@kernel.org, alexander.shishkin@linux.intel.com, andrew.kilroy@arm.com, benh@kernel.crashing.org, james.clark@arm.com, john.garry@huawei.com, jolsa@kernel.org, kjain@linux.ibm.com, lihuafei1@huawei.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, mark.rutland@arm.com, mathieu.poirier@linaro.org, mingo@redhat.com, namhyung@kernel.org, peterz@infradead.org, will@kernel.org, yao.jin@linux.intel.com, Nick.Forrington@arm.com Subject: Re: [PATCH v2 2/2] perf mem: Support HITM for when mem_lvl_num is used Message-ID: <20220316124208.GA310478@leoy-ThinkPad-X240s> References: <20220314183721.3198-1-alisaidi@amazon.com> <172ce478-b539-2aa4-0470-1b96c6b8169b@arm.com> <7b3aaa4d-5194-a729-f8ad-d55ada7fa58f@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <7b3aaa4d-5194-a729-f8ad-d55ada7fa58f@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220316_054219_065265_CB526914 X-CRM114-Status: GOOD ( 15.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Mar 16, 2022 at 11:43:52AM +0000, German Gomez wrote: [...] > >>> I had a look at the TRMs for the N1[1], V1[2] and N2[3] Neoverse cores > >>> (specifically the LL_CACHE_RD pmu events). If we were to assign a number > >>> to the system cache (assuming all caches are implemented): > >>> > >>> *For N1*, if L2 and L3 are implemented, system cache would follow at *L4* > >> To date no one has built 4 level though. Everyone has only built three. > > The N1SDP board advertises 4 levels (we use it regularly for testing perf patches) > > That said, it's probably the odd one out. > > I'm not against assuming 3 levels. Later if there's is a strong need for L4, indeed we can go back and change it. Thanks for the info. For exploring cache hierarchy via sysFS is a good idea, the only one concern for me is: can we simply take the system cache as the same thing as the highest level cache? If so, I think another option is to define a cache level as "PERF_MEM_LVLNUM_SYSTEM_CACHE" and extend the decoding code for support it. With PERF_MEM_LVLNUM_SYSTEM_CACHE, it can tell users clearly the data source from system cache, and users can easily map this info with the cache media on the working platform. In practice, I don't object to use cache level 3 at first step. At least this can meet the requirement at current stage. Thanks, Leo _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel