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Fri, 25 Mar 2022 23:23:11 -0700 (PDT) Date: Sat, 26 Mar 2022 14:23:03 +0800 From: Leo Yan To: Ali Saidi Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-arm-kernel@lists.infradead.org, german.gomez@arm.com, acme@kernel.org, benh@kernel.crashing.org, Nick.Forrington@arm.com, alexander.shishkin@linux.intel.com, andrew.kilroy@arm.com, james.clark@arm.com, john.garry@huawei.com, jolsa@kernel.org, kjain@linux.ibm.com, lihuafei1@huawei.com, mark.rutland@arm.com, mathieu.poirier@linaro.org, mingo@redhat.com, namhyung@kernel.org, peterz@infradead.org, will@kernel.org Subject: Re: [PATCH v4 4/4] perf mem: Support HITM for when mem_lvl_num is any Message-ID: <20220326062303.GC20556@leoy-ThinkPad-X240s> References: <20220324183323.31414-1-alisaidi@amazon.com> <20220324183323.31414-5-alisaidi@amazon.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220324183323.31414-5-alisaidi@amazon.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220325_232313_355441_44F2F1C2 X-CRM114-Status: GOOD ( 22.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Mar 24, 2022 at 06:33:23PM +0000, Ali Saidi wrote: > For loads that hit in a the LLC snoop filter and are fulfilled from a > higher level cache on arm64 Neoverse cores, it's not usually clear what > the true level of the cache the data came from (i.e. a transfer from a > core could come from it's L1 or L2). Instead of making an assumption of > where the line came from, add support for incrementing HITM if the > source is CACHE_ANY. > > Since other architectures don't seem to populate the mem_lvl_num field > here there shouldn't be a change in functionality. > > Signed-off-by: Ali Saidi > Tested-by: German Gomez > Reviewed-by: German Gomez > --- > tools/perf/util/mem-events.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c > index e5e405185498..084977cfebef 100644 > --- a/tools/perf/util/mem-events.c > +++ b/tools/perf/util/mem-events.c > @@ -539,6 +539,15 @@ do { \ > stats->ld_llchit++; > } > > + /* > + * A hit in another cores cache must mean a llc snoop > + * filter hit > + */ > + if (lnum == P(LVLNUM, ANY_CACHE)) { > + if (snoop & P(SNOOP, HITM)) > + HITM_INC(lcl_hitm); > + } This might break the memory profiling result for x86, see file arch/x86/events/intel/ds.c: 97 void __init intel_pmu_pebs_data_source_skl(bool pmem) 98 { 99 u64 pmem_or_l4 = pmem ? LEVEL(PMEM) : LEVEL(L4); ... 105 pebs_data_source[0x0d] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM); 106 } Which means that it's possible that it's a remote access and the cache level is ANY_CACHE, it's good to add checking for bit PERF_MEM_REMOTE_REMOTE: u64 remote = data_src->mem_remote; /* * A hit in another cores cache must mean a llc snoop * filter hit */ if (lnum == P(LVLNUM, ANY_CACHE) && remote != P(REMOTE, REMOTE)) { if (snoop & P(SNOOP, HITM)) HITM_INC(lcl_hitm); } Appreciate German's reviewing and testing, and sorry I jumped in very late. Thanks, Leo > + > if (lvl & P(LVL, LOC_RAM) || lnum == P(LVLNUM, RAM)) { > stats->lcl_dram++; > if (snoop & P(SNOOP, HIT)) > -- > 2.32.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel