[PATCH 0/3] Ensure Low period of SCL is correct

From: Lucas Tanure <tanure@linux.com>
To: Neil Armstrong <narmstrong@baylibre.com>,
	Kevin Hilman <khilman@baylibre.com>,
	Jerome Brunet <jbrunet@baylibre.com>,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
	Lucas Tanure <tanure@linux.com>
Subject: [PATCH 0/3] Ensure Low period of SCL is correct
Date: Sat, 26 Mar 2022 10:22:26 +0000	[thread overview]
Message-ID: <20220326102229.421718-1-tanure@linux.com> (raw)

The default duty cycle of 33% is less than the required
by the I2C specs for the LOW period of the SCL clock.

So, for 100Khz or less, use 50%H/50%L duty cycle, and
for the clock above 100Khz, use 40%H/60%L duty cycle.
That ensures the low period of SCL is always more than
the minimum required by the specs at any given frequency.

Lucas Tanure (3):
  i2c: meson: Use _SHIFT and _MASK for register definitions
  i2c: meson: Use 50% duty cycle for I2C clock
  i2c: meson: Remove meson_i2c_data

 drivers/i2c/busses/i2c-meson.c | 104 ++++++++++++++++++---------------
 1 file changed, 56 insertions(+), 48 deletions(-)

-- 
2.35.1

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