From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D676AC433F5 for ; Wed, 30 Mar 2022 08:24:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:CC:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=A199o0CpkQ12F1fU+ORZMzv97cgY1p+Rh/yDMNGG+qg=; b=ludAEAmxc/deqL lMN8r93Fjb0xUTZDilKxJNW46KBZB6qepfVk8buzGe4Ba1ZQOpxOKDhO+Cczt8F5IwI6V2iH2o4cW YMGtA4R1vvAPucL+WlGqmid6u0tY/7Rz8pApaLQjNZNP8NZY4NEVrcuHLCnM50AW4yRDxeGfXqrex iET+j+12AhJvZppCNP2fxptXlw7ya4DUfzc6tSz7esW9z+cQpWMfBPqTHtvG3YCewu4455eEaXGbi cHWPGeAfkFf+GEkAzvPI8ytVnOh+4Y7nkT7uA0ZMdEQXdg8y1MqdbhqlTnLimwr6m/P+ux0DMq/mq geyPhl7I5QLgbpI+vkOw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nZTbU-00EneB-4c; Wed, 30 Mar 2022 08:22:56 +0000 Received: from smtp2.axis.com ([195.60.68.18]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nZTaG-00EmzE-UR for linux-arm-kernel@lists.infradead.org; Wed, 30 Mar 2022 08:21:42 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; q=dns/txt; s=axis-central1; t=1648628501; x=1680164501; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=AH+4xQbZM08WZt8qm/l3tTz+5fAhec0WZ52E5BgUGxc=; b=W/PD1TKhOhgZf428OV4q61BavHO1W8MZlZZ/te78oWgG/hBKAlXiu/Lj /jtgdpMhNSY8eT9lB/2rE/6Txh7RLvAp9sKTPl/uhbtA/mW9z6aEzqr1M TZLDmQ0B0sd48MBaPhOIwIC4cVPME3S0/SwGcVy0B6O8/AcfZF5x3JNt4 LUqEXuwRpKA2aEGI2gDmwuaSyQM9q/v+L/Eb9Ff9eDdi8F4Pnbam4GxvE ZEgbXVTPsZm/2Ah0heJV/xjoYp3h2N7j+rQJoKz81ByCkI4fYqnbufyqC 1hKGEz8ndeechYBuILOdyhRL4c5njmSqA/rIrLeAPHcQcmRy34q/JP1sR Q==; Date: Wed, 30 Mar 2022 10:21:37 +0200 From: Vincent Whitchurch To: Marek Szyprowski CC: Krzysztof Kozlowski , "tglx@linutronix.de" , "daniel.lezcano@linaro.org" , kernel , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-samsung-soc@vger.kernel.org" , "devicetree@vger.kernel.org" , "alim.akhtar@samsung.com" , "robh+dt@kernel.org" Subject: Re: [PATCH v2 3/4] clocksource/drivers/exynos_mct: Support local-timer-index property Message-ID: <20220330082137.GA21079@axis.com> References: <20220308142410.3193729-1-vincent.whitchurch@axis.com> <20220308142410.3193729-4-vincent.whitchurch@axis.com> <226dcb1b-d141-f0d3-68c4-11d2466ca571@canonical.com> <20220311113543.GA17877@axis.com> <69be9f88-b69b-c149-4387-c5002219bf0a@canonical.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220330_012141_438613_8D85DD72 X-CRM114-Status: GOOD ( 15.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Mar 21, 2022 at 09:00:08AM +0100, Marek Szyprowski wrote: > Right, I've played a bit with MCT on some older Exynos SoCs (ARM 32bit > based and even Exynos5433) and it looked that none of it enabled MCT FRC > timer in their proprietary firmware. I've even proposed a patch for this > once ([1]), but such approach has been rejected. I think that calling > exynos4_mct_frc_start() unconditionally won't hurt. Thank you for looking into this. The proposal was however not to avoid changing when exynos4_mct_frc_start() is called, but to instead skip the write to the Timer Enable bit of the G_TCON register if it is already set, like in the below patch. (This is needed to avoid races when the FRC is shared between CPUs in an AMP configuration, since TCON can be modified for other reasons from the CPU which is using the global comparator.) If I understand your comment correctly, such a change should not cause any difference at least on the platforms you looked at since there MCT_G_TCON_START will not have been set at startup. diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index 6db3d5511b0f..ed462e0a77ff 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -162,6 +162,9 @@ static void exynos4_mct_frc_start(void) u32 reg; reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); + if (reg & MCT_G_TCON_START) + return; + reg |= MCT_G_TCON_START; exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); } _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel