From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Richard Schleich <rs@noreya.tech>,
Stefan Wahren <stefan.wahren@i2se.com>,
Florian Fainelli <f.fainelli@gmail.com>,
Sasha Levin <sashal@kernel.org>,
robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH AUTOSEL 5.10 21/37] ARM: dts: bcm2711: Add the missing L1/L2 cache information
Date: Wed, 30 Mar 2022 07:51:06 -0400 [thread overview]
Message-ID: <20220330115122.1671763-21-sashal@kernel.org> (raw)
In-Reply-To: <20220330115122.1671763-1-sashal@kernel.org>
From: Richard Schleich <rs@noreya.tech>
[ Upstream commit 618682b350990f8f1bee718949c4b3858711eb58 ]
This patch fixes the kernel warning
"cacheinfo: Unable to detect cache hierarchy for CPU 0"
for the bcm2711 on newer kernel versions.
Signed-off-by: Richard Schleich <rs@noreya.tech>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
[florian: Align and remove comments matching property values]
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
arch/arm/boot/dts/bcm2711.dtsi | 50 ++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
index e46a3f4ad350..b50229c3102f 100644
--- a/arch/arm/boot/dts/bcm2711.dtsi
+++ b/arch/arm/boot/dts/bcm2711.dtsi
@@ -433,12 +433,26 @@
#size-cells = <0>;
enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
+ /* Source for d/i-cache-line-size and d/i-cache-sets
+ * https://developer.arm.com/documentation/100095/0003
+ * /Level-1-Memory-System/About-the-L1-memory-system?lang=en
+ * Source for d/i-cache-size
+ * https://www.raspberrypi.com/documentation/computers
+ * /processors.html#bcm2711
+ */
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000d8>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
+ next-level-cache = <&l2>;
};
cpu1: cpu@1 {
@@ -447,6 +461,13 @@
reg = <1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000e0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
+ next-level-cache = <&l2>;
};
cpu2: cpu@2 {
@@ -455,6 +476,13 @@
reg = <2>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000e8>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
+ next-level-cache = <&l2>;
};
cpu3: cpu@3 {
@@ -463,6 +491,28 @@
reg = <3>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000f0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
+ next-level-cache = <&l2>;
+ };
+
+ /* Source for d/i-cache-line-size and d/i-cache-sets
+ * https://developer.arm.com/documentation/100095/0003
+ * /Level-2-Memory-System/About-the-L2-memory-system?lang=en
+ * Source for d/i-cache-size
+ * https://www.raspberrypi.com/documentation/computers
+ * /processors.html#bcm2711
+ */
+ l2: l2-cache0 {
+ compatible = "cache";
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set
+ cache-level = <2>;
};
};
--
2.34.1
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next prev parent reply other threads:[~2022-03-30 12:28 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20220330115122.1671763-1-sashal@kernel.org>
2022-03-30 11:50 ` [PATCH AUTOSEL 5.10 10/37] ARM: dts: qcom: fix gic_irq_domain_translate warnings for msm8960 Sasha Levin
2022-03-30 11:50 ` [PATCH AUTOSEL 5.10 11/37] ARM: dts: bcm2837: Add the missing L1/L2 cache information Sasha Levin
2022-03-30 11:51 ` [PATCH AUTOSEL 5.10 15/37] ARM: ftrace: avoid redundant loads or clobbering IP Sasha Levin
2022-03-30 11:51 ` [PATCH AUTOSEL 5.10 16/37] ARM: dts: imx7: Use audio_mclk_post_div instead audio_mclk_root_clk Sasha Levin
2022-03-30 11:51 ` [PATCH AUTOSEL 5.10 17/37] arm64: defconfig: build imx-sdma as a module Sasha Levin
2022-03-30 11:51 ` Sasha Levin [this message]
2022-03-30 11:51 ` [PATCH AUTOSEL 5.10 26/37] uaccess: fix type mismatch warnings from access_ok() Sasha Levin
2022-03-30 11:51 ` [PATCH AUTOSEL 5.10 28/37] ARM: tegra: tamonten: Fix I2C3 pad setting Sasha Levin
2022-03-30 11:51 ` [PATCH AUTOSEL 5.10 29/37] ARM: mmp: Fix failure to remove sram device Sasha Levin
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