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[109.49.33.111]) by smtp.gmail.com with ESMTPSA id az19-20020a05600c601300b0038cadf3aa69sm11622812wmb.36.2022.03.31.08.45.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Mar 2022 08:45:46 -0700 (PDT) From: Rui Miguel Silva To: Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Rui Miguel Silva Subject: [PATCH v4 0/3] arm64: dts: add corstone1000 device tree Date: Thu, 31 Mar 2022 16:45:33 +0100 Message-Id: <20220331154536.1544220-1-rui.silva@linaro.org> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220331_084549_181374_C736AAB9 X-CRM114-Status: GOOD ( 12.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add device tree and correspondent binding for ARM corstone1000 [0] platform for FVP (Fixed Virtual Platform) and FPGA MPS3 prototyping board implementation of this system. Cheers, Rui v3 [3] ->v4: Sudeep Holla: - replace documentation links to permanent ones - extend l2 cache properties - move cpu definition to dtsi since the FVP is also a cortex-a35 implementation - remove unneeded interrupt parents from uart v2 [2] ->v3: Rob Herring: - unevaluatedProperties fix - running dtbs_check had a fatal error: dpu-qcm2290.example.dts:23:18: which make it exit before the smsc,lan91c111 was verified. Fixed the issue in smsc,lan91c111 example by adding arm-gic header Andrew Lunn: - remove lan91c111 txt file since we are replacing it with a schema one. v1 [1] ->v2: Rob Herring: - change license to dual - distinguish cpu entry for fvp and mps3 - mmio nodes in simple-bus - refactor mhu entries - add secure-status to secure world only accessible mhu - add smsc,lan91c111 binding patch to avoid dtbs_check warnings Marc Zyngier: - fixed SPI cpu mask invalid entries - reduce the mask to the existing cpu count (4->1) - change one interrupt to symbolic enconding 0: https://developer.arm.com/documentation/102360/0000 1: https://lore.kernel.org/linux-devicetree/20220325133655.4177977-1-rui.silva@linaro.org/ 2: https://lore.kernel.org/linux-devicetree/20220329213519.801033-1-rui.silva@linaro.org/ 3: https://lore.kernel.org/linux-devicetree/20220330131053.1122502-1-rui.silva@linaro.org/ Rui Miguel Silva (3): dt-bindings: net: smsc,lan91c111 convert to schema dt-bindings: arm: add corstone1000 platform arm64: dts: arm: add corstone1000 device tree .../bindings/arm/arm,corstone1000.yaml | 45 +++++ .../bindings/net/smsc,lan91c111.yaml | 61 +++++++ .../bindings/net/smsc-lan91c111.txt | 17 -- arch/arm64/boot/dts/arm/Makefile | 1 + arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 23 +++ arch/arm64/boot/dts/arm/corstone1000-mps3.dts | 32 ++++ arch/arm64/boot/dts/arm/corstone1000.dtsi | 164 ++++++++++++++++++ 7 files changed, 326 insertions(+), 17 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/arm,corstone1000.yaml create mode 100644 Documentation/devicetree/bindings/net/smsc,lan91c111.yaml delete mode 100644 Documentation/devicetree/bindings/net/smsc-lan91c111.txt create mode 100644 arch/arm64/boot/dts/arm/corstone1000-fvp.dts create mode 100644 arch/arm64/boot/dts/arm/corstone1000-mps3.dts create mode 100644 arch/arm64/boot/dts/arm/corstone1000.dtsi -- 2.35.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel