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[68.147.0.187]) by smtp.gmail.com with ESMTPSA id p4-20020a637404000000b00375948e63d6sm10641282pgc.91.2022.04.04.09.15.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Apr 2022 09:15:56 -0700 (PDT) Date: Mon, 4 Apr 2022 10:15:54 -0600 From: Mathieu Poirier To: Mike Leach Cc: suzuki.poulose@arm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org Subject: Re: [PATCH 00/10] coresight: Add new API to allocate trace source ID values Message-ID: <20220404161554.GA4079910@p14s> References: <20220308205000.27646-1-mike.leach@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220308205000.27646-1-mike.leach@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220404_091558_382305_A76BBE47 X-CRM114-Status: GOOD ( 31.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Good morning, On Tue, Mar 08, 2022 at 08:49:50PM +0000, Mike Leach wrote: > The current method for allocating trace source ID values to sources is > to use a fixed algorithm for CPU based sources of (cpu_num * 2 + 0x10). > The STM is allocated ID 0x1. > > This fixed algorithm is used in both the CoreSight driver code, and by > perf when writing the trace metadata in the AUXTRACE_INFO record. > > The method needs replacing as currently:- > 1. It is inefficient in using available IDs. > 2. Does not scale to larger systems with many cores and the algorithm > has no limits so will generate invalid trace IDs for cpu number > 44. > > Additionally requirements to allocate additional system IDs on some > systems have been seen. > > This patch set introduces an API that allows the allocation of trace IDs > in a dynamic manner. > > Architecturally reserved IDs are never allocated, and the system is > limited to allocating only valid IDs. > > Each of the current trace sources ETM3.x, ETM4.x and STM is updated to use > the new API. > > perf handling is changed so that the ID associated with the CPU is read > from sysfs. The ID allocator is notified when perf events start and stop > so CPU based IDs are kept constant throughout any perf session. > > For the ETMx.x devices IDs are allocated on certain events > a) When using sysfs, an ID will be allocated on hardware enable, and freed > when the sysfs reset is written. > b) When using perf, ID is allocated on hardware enable, and freed on > hardware disable. > > For both cases the ID is allocated when sysfs is read to get the current > trace ID. This ensures that consistent decode metadata can be extracted > from the system where this read occurs before device enable. > > Note: This patchset breaks backward compatibility for perf record. > Because the method for generating the AUXTRACE_INFO meta data has > changed, using an older perf record will result in metadata that > does not match the trace IDs used in the recorded trace data. > This mismatch will cause subsequent decode to fail. Older versions of > perf will still be able to decode data generated by the updated system. > I have started looking at this set, comments to follow shortly. Thanks, Mathieu > > Applies to coresight/next [b54f53bc11a5] > Tested on DB410c > > Mike Leach (10): > coresight: trace-id: Add API to dynamically assign trace ID values > coresight: trace-id: Set up source trace ID map for system > coresight: stm: Update STM driver to use Trace ID api > coresight: etm4x: Use trace ID API to dynamically allocate trace ID > coresight: etm3x: Use trace ID API to allocate IDs > coresight: perf: traceid: Add perf notifiers for trace ID > perf: cs-etm: Update event to read trace ID from sysfs > coresight: Remove legacy Trace ID allocation mechanism > coresight: etmX.X: stm: Remove unused legacy source trace ID ops > coresight: trace-id: Add debug & test macros to trace id allocation > > drivers/hwtracing/coresight/Makefile | 2 +- > drivers/hwtracing/coresight/coresight-core.c | 64 ++--- > .../hwtracing/coresight/coresight-etm-perf.c | 16 +- > drivers/hwtracing/coresight/coresight-etm.h | 3 +- > .../coresight/coresight-etm3x-core.c | 93 ++++--- > .../coresight/coresight-etm3x-sysfs.c | 28 +- > .../coresight/coresight-etm4x-core.c | 63 ++++- > .../coresight/coresight-etm4x-sysfs.c | 32 ++- > drivers/hwtracing/coresight/coresight-etm4x.h | 3 + > drivers/hwtracing/coresight/coresight-priv.h | 1 + > drivers/hwtracing/coresight/coresight-stm.c | 49 +--- > .../hwtracing/coresight/coresight-trace-id.c | 255 ++++++++++++++++++ > .../hwtracing/coresight/coresight-trace-id.h | 69 +++++ > include/linux/coresight-pmu.h | 12 - > include/linux/coresight.h | 3 - > tools/perf/arch/arm/util/cs-etm.c | 12 +- > 16 files changed, 530 insertions(+), 175 deletions(-) > create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.c > create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.h > > -- > 2.17.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel