* [PATCH v4 0/5] i.MX8MP GPC
@ 2022-03-30 10:46 Lucas Stach
2022-03-30 10:46 ` [PATCH v4 1/5] soc: imx: gpcv2: add PGC control register indirection Lucas Stach
` (5 more replies)
0 siblings, 6 replies; 11+ messages in thread
From: Lucas Stach @ 2022-03-30 10:46 UTC (permalink / raw)
To: Shawn Guo
Cc: Pengutronix Kernel Team, NXP Linux Team, Rob Herring, Marek Vasut,
Laurent Pinchart, Alexander Stein, Fabio Estevam,
linux-arm-kernel, devicetree, patchwork-lst
Hi Shawn,
This is mostly a resend with all the reviews, acks and testing
tags applied. I dropped the HSIO blk-ctrl part from this series,
as I noticed that this needs some rework to better fit the
upcoming HDMI blk-ctrl. The GPC part is still complete, so the
MEDIA blk-ctrl series from Laurent can be applied on top of this
v4.
Regards,
Lucas
Lucas Stach (5):
soc: imx: gpcv2: add PGC control register indirection
dt-bindings: power: add defines for i.MX8MP power domain
soc: imx: gpcv2: add support for i.MX8MP power domains
arm64: dts: imx8mp: add GPC node with GPU power domains
arm64: dts: imx8mp: add GPU nodes
.../bindings/power/fsl,imx-gpcv2.yaml | 2 +
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 72 +++
drivers/soc/imx/gpcv2.c | 430 +++++++++++++++++-
include/dt-bindings/power/imx8mp-power.h | 29 ++
4 files changed, 521 insertions(+), 12 deletions(-)
create mode 100644 include/dt-bindings/power/imx8mp-power.h
--
2.30.2
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^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH v4 1/5] soc: imx: gpcv2: add PGC control register indirection 2022-03-30 10:46 [PATCH v4 0/5] i.MX8MP GPC Lucas Stach @ 2022-03-30 10:46 ` Lucas Stach 2022-03-30 10:46 ` [PATCH v4 2/5] dt-bindings: power: add defines for i.MX8MP power domain Lucas Stach ` (4 subsequent siblings) 5 siblings, 0 replies; 11+ messages in thread From: Lucas Stach @ 2022-03-30 10:46 UTC (permalink / raw) To: Shawn Guo Cc: Pengutronix Kernel Team, NXP Linux Team, Rob Herring, Marek Vasut, Laurent Pinchart, Alexander Stein, Fabio Estevam, linux-arm-kernel, devicetree, patchwork-lst The PGC control registers in the shared (not per-PGC) region of the GPC address space have different offsets on i.MX8MP to make space for additional interrupt control registers. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> --- drivers/soc/imx/gpcv2.c | 43 ++++++++++++++++++++++++++++++----------- 1 file changed, 32 insertions(+), 11 deletions(-) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 3cb123016b3e..677c5c581521 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -184,9 +184,17 @@ #define GPC_PGC_CTRL_PCR BIT(0) +struct imx_pgc_regs { + u16 map; + u16 pup; + u16 pdn; + u16 hsk; +}; + struct imx_pgc_domain { struct generic_pm_domain genpd; struct regmap *regmap; + const struct imx_pgc_regs *regs; struct regulator *regulator; struct reset_control *reset; struct clk_bulk_data *clks; @@ -210,6 +218,7 @@ struct imx_pgc_domain_data { const struct imx_pgc_domain *domains; size_t domains_num; const struct regmap_access_table *reg_access_table; + const struct imx_pgc_regs *pgc_regs; }; static inline struct imx_pgc_domain * @@ -249,14 +258,14 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) if (domain->bits.pxx) { /* request the domain to power up */ - regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, + regmap_update_bits(domain->regmap, domain->regs->pup, domain->bits.pxx, domain->bits.pxx); /* * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait * for PUP_REQ/PDN_REQ bit to be cleared */ ret = regmap_read_poll_timeout(domain->regmap, - GPC_PU_PGC_SW_PUP_REQ, reg_val, + domain->regs->pup, reg_val, !(reg_val & domain->bits.pxx), 0, USEC_PER_MSEC); if (ret) { @@ -278,11 +287,11 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) /* request the ADB400 to power up */ if (domain->bits.hskreq) { - regmap_update_bits(domain->regmap, GPC_PU_PWRHSK, + regmap_update_bits(domain->regmap, domain->regs->hsk, domain->bits.hskreq, domain->bits.hskreq); /* - * ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK, reg_val, + * ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk, reg_val, * (reg_val & domain->bits.hskack), 0, * USEC_PER_MSEC); * Technically we need the commented code to wait handshake. But that needs @@ -329,10 +338,10 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd) /* request the ADB400 to power down */ if (domain->bits.hskreq) { - regmap_clear_bits(domain->regmap, GPC_PU_PWRHSK, + regmap_clear_bits(domain->regmap, domain->regs->hsk, domain->bits.hskreq); - ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK, + ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk, reg_val, !(reg_val & domain->bits.hskack), 0, USEC_PER_MSEC); @@ -350,14 +359,14 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd) } /* request the domain to power down */ - regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ, + regmap_update_bits(domain->regmap, domain->regs->pdn, domain->bits.pxx, domain->bits.pxx); /* * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait * for PUP_REQ/PDN_REQ bit to be cleared */ ret = regmap_read_poll_timeout(domain->regmap, - GPC_PU_PGC_SW_PDN_REQ, reg_val, + domain->regs->pdn, reg_val, !(reg_val & domain->bits.pxx), 0, USEC_PER_MSEC); if (ret) { @@ -442,10 +451,18 @@ static const struct regmap_access_table imx7_access_table = { .n_yes_ranges = ARRAY_SIZE(imx7_yes_ranges), }; +static const struct imx_pgc_regs imx7_pgc_regs = { + .map = GPC_PGC_CPU_MAPPING, + .pup = GPC_PU_PGC_SW_PUP_REQ, + .pdn = GPC_PU_PGC_SW_PDN_REQ, + .hsk = GPC_PU_PWRHSK, +}; + static const struct imx_pgc_domain_data imx7_pgc_domain_data = { .domains = imx7_pgc_domains, .domains_num = ARRAY_SIZE(imx7_pgc_domains), .reg_access_table = &imx7_access_table, + .pgc_regs = &imx7_pgc_regs, }; static const struct imx_pgc_domain imx8m_pgc_domains[] = { @@ -614,6 +631,7 @@ static const struct imx_pgc_domain_data imx8m_pgc_domain_data = { .domains = imx8m_pgc_domains, .domains_num = ARRAY_SIZE(imx8m_pgc_domains), .reg_access_table = &imx8m_access_table, + .pgc_regs = &imx7_pgc_regs, }; static const struct imx_pgc_domain imx8mm_pgc_domains[] = { @@ -804,6 +822,7 @@ static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = { .domains = imx8mm_pgc_domains, .domains_num = ARRAY_SIZE(imx8mm_pgc_domains), .reg_access_table = &imx8mm_access_table, + .pgc_regs = &imx7_pgc_regs, }; static const struct imx_pgc_domain imx8mn_pgc_domains[] = { @@ -895,6 +914,7 @@ static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = { .domains = imx8mn_pgc_domains, .domains_num = ARRAY_SIZE(imx8mn_pgc_domains), .reg_access_table = &imx8mn_access_table, + .pgc_regs = &imx7_pgc_regs, }; static int imx_pgc_domain_probe(struct platform_device *pdev) @@ -927,7 +947,7 @@ static int imx_pgc_domain_probe(struct platform_device *pdev) pm_runtime_enable(domain->dev); if (domain->bits.map) - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + regmap_update_bits(domain->regmap, domain->regs->map, domain->bits.map, domain->bits.map); ret = pm_genpd_init(&domain->genpd, NULL, true); @@ -953,7 +973,7 @@ static int imx_pgc_domain_probe(struct platform_device *pdev) pm_genpd_remove(&domain->genpd); out_domain_unmap: if (domain->bits.map) - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + regmap_update_bits(domain->regmap, domain->regs->map, domain->bits.map, 0); pm_runtime_disable(domain->dev); @@ -968,7 +988,7 @@ static int imx_pgc_domain_remove(struct platform_device *pdev) pm_genpd_remove(&domain->genpd); if (domain->bits.map) - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + regmap_update_bits(domain->regmap, domain->regs->map, domain->bits.map, 0); pm_runtime_disable(domain->dev); @@ -1099,6 +1119,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev) domain = pd_pdev->dev.platform_data; domain->regmap = regmap; + domain->regs = domain_data->pgc_regs; domain->genpd.power_on = imx_pgc_power_up; domain->genpd.power_off = imx_pgc_power_down; -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v4 2/5] dt-bindings: power: add defines for i.MX8MP power domain 2022-03-30 10:46 [PATCH v4 0/5] i.MX8MP GPC Lucas Stach 2022-03-30 10:46 ` [PATCH v4 1/5] soc: imx: gpcv2: add PGC control register indirection Lucas Stach @ 2022-03-30 10:46 ` Lucas Stach 2022-04-08 13:26 ` Shawn Guo 2022-03-30 10:46 ` [PATCH v4 3/5] soc: imx: gpcv2: add support for i.MX8MP power domains Lucas Stach ` (3 subsequent siblings) 5 siblings, 1 reply; 11+ messages in thread From: Lucas Stach @ 2022-03-30 10:46 UTC (permalink / raw) To: Shawn Guo Cc: Pengutronix Kernel Team, NXP Linux Team, Rob Herring, Marek Vasut, Laurent Pinchart, Alexander Stein, Fabio Estevam, linux-arm-kernel, devicetree, patchwork-lst This adds the DT defines for the GPC power domains found on the i.MX8MP SoC. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> --- .../bindings/power/fsl,imx-gpcv2.yaml | 2 ++ include/dt-bindings/power/imx8mp-power.h | 29 +++++++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 include/dt-bindings/power/imx8mp-power.h diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml index 01bdda167eef..747622bdc57b 100644 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml @@ -28,6 +28,7 @@ properties: - fsl,imx8mn-gpc - fsl,imx8mq-gpc - fsl,imx8mm-gpc + - fsl,imx8mp-gpc reg: maxItems: 1 @@ -57,6 +58,7 @@ properties: include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc include/dt-bindings/power/imx8mm-power.h for fsl,imx8mm-gpc + include/dt-bindings/power/imx8mp-power.h for fsl,imx8mp-gpc maxItems: 1 clocks: diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h new file mode 100644 index 000000000000..7c67689e4faf --- /dev/null +++ b/include/dt-bindings/power/imx8mp-power.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2020 Pengutronix, Sascha Hauer <kernel@pengutronix.de> + */ + +#ifndef __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__ +#define __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__ + +#define IMX8MP_POWER_DOMAIN_MIPI_PHY1 0 +#define IMX8MP_POWER_DOMAIN_PCIE_PHY 1 +#define IMX8MP_POWER_DOMAIN_USB1_PHY 2 +#define IMX8MP_POWER_DOMAIN_USB2_PHY 3 +#define IMX8MP_POWER_DOMAIN_MLMIX 4 +#define IMX8MP_POWER_DOMAIN_AUDIOMIX 5 +#define IMX8MP_POWER_DOMAIN_GPU2D 6 +#define IMX8MP_POWER_DOMAIN_GPUMIX 7 +#define IMX8MP_POWER_DOMAIN_VPUMIX 8 +#define IMX8MP_POWER_DOMAIN_GPU3D 9 +#define IMX8MP_POWER_DOMAIN_MEDIAMIX 10 +#define IMX8MP_POWER_DOMAIN_VPU_G1 11 +#define IMX8MP_POWER_DOMAIN_VPU_G2 12 +#define IMX8MP_POWER_DOMAIN_VPU_VC8000E 13 +#define IMX8MP_POWER_DOMAIN_HDMIMIX 14 +#define IMX8MP_POWER_DOMAIN_HDMI_PHY 15 +#define IMX8MP_POWER_DOMAIN_MIPI_PHY2 16 +#define IMX8MP_POWER_DOMAIN_HSIOMIX 17 +#define IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP 18 + +#endif -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v4 2/5] dt-bindings: power: add defines for i.MX8MP power domain 2022-03-30 10:46 ` [PATCH v4 2/5] dt-bindings: power: add defines for i.MX8MP power domain Lucas Stach @ 2022-04-08 13:26 ` Shawn Guo 0 siblings, 0 replies; 11+ messages in thread From: Shawn Guo @ 2022-04-08 13:26 UTC (permalink / raw) To: Lucas Stach Cc: Pengutronix Kernel Team, NXP Linux Team, Rob Herring, Marek Vasut, Laurent Pinchart, Alexander Stein, Fabio Estevam, linux-arm-kernel, devicetree, patchwork-lst On Wed, Mar 30, 2022 at 12:46:17PM +0200, Lucas Stach wrote: > This adds the DT defines for the GPC power domains found on the > i.MX8MP SoC. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > Acked-by: Rob Herring <robh@kernel.org> This one has landed into v5.18-rc1, so only applied the rest. Shawn _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v4 3/5] soc: imx: gpcv2: add support for i.MX8MP power domains 2022-03-30 10:46 [PATCH v4 0/5] i.MX8MP GPC Lucas Stach 2022-03-30 10:46 ` [PATCH v4 1/5] soc: imx: gpcv2: add PGC control register indirection Lucas Stach 2022-03-30 10:46 ` [PATCH v4 2/5] dt-bindings: power: add defines for i.MX8MP power domain Lucas Stach @ 2022-03-30 10:46 ` Lucas Stach 2022-03-30 10:46 ` [PATCH v4 4/5] arm64: dts: imx8mp: add GPC node with GPU " Lucas Stach ` (2 subsequent siblings) 5 siblings, 0 replies; 11+ messages in thread From: Lucas Stach @ 2022-03-30 10:46 UTC (permalink / raw) To: Shawn Guo Cc: Pengutronix Kernel Team, NXP Linux Team, Rob Herring, Marek Vasut, Laurent Pinchart, Alexander Stein, Fabio Estevam, linux-arm-kernel, devicetree, patchwork-lst This adds driver support for all the GPC power domains found on the i.MX8MP SoC. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> --- drivers/soc/imx/gpcv2.c | 387 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 386 insertions(+), 1 deletion(-) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 677c5c581521..85aa86e1338a 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -21,10 +21,12 @@ #include <dt-bindings/power/imx8mq-power.h> #include <dt-bindings/power/imx8mm-power.h> #include <dt-bindings/power/imx8mn-power.h> +#include <dt-bindings/power/imx8mp-power.h> #define GPC_LPCR_A_CORE_BSC 0x000 #define GPC_PGC_CPU_MAPPING 0x0ec +#define IMX8MP_GPC_PGC_CPU_MAPPING 0x1cc #define IMX7_USB_HSIC_PHY_A_CORE_DOMAIN BIT(6) #define IMX7_USB_OTG2_PHY_A_CORE_DOMAIN BIT(5) @@ -65,6 +67,29 @@ #define IMX8MN_OTG1_A53_DOMAIN BIT(4) #define IMX8MN_MIPI_A53_DOMAIN BIT(2) +#define IMX8MP_MEDIA_ISPDWP_A53_DOMAIN BIT(20) +#define IMX8MP_HSIOMIX_A53_DOMAIN BIT(19) +#define IMX8MP_MIPI_PHY2_A53_DOMAIN BIT(18) +#define IMX8MP_HDMI_PHY_A53_DOMAIN BIT(17) +#define IMX8MP_HDMIMIX_A53_DOMAIN BIT(16) +#define IMX8MP_VPU_VC8000E_A53_DOMAIN BIT(15) +#define IMX8MP_VPU_G2_A53_DOMAIN BIT(14) +#define IMX8MP_VPU_G1_A53_DOMAIN BIT(13) +#define IMX8MP_MEDIAMIX_A53_DOMAIN BIT(12) +#define IMX8MP_GPU3D_A53_DOMAIN BIT(11) +#define IMX8MP_VPUMIX_A53_DOMAIN BIT(10) +#define IMX8MP_GPUMIX_A53_DOMAIN BIT(9) +#define IMX8MP_GPU2D_A53_DOMAIN BIT(8) +#define IMX8MP_AUDIOMIX_A53_DOMAIN BIT(7) +#define IMX8MP_MLMIX_A53_DOMAIN BIT(6) +#define IMX8MP_USB2_PHY_A53_DOMAIN BIT(5) +#define IMX8MP_USB1_PHY_A53_DOMAIN BIT(4) +#define IMX8MP_PCIE_PHY_A53_DOMAIN BIT(3) +#define IMX8MP_MIPI_PHY1_A53_DOMAIN BIT(2) + +#define IMX8MP_GPC_PU_PGC_SW_PUP_REQ 0x0d8 +#define IMX8MP_GPC_PU_PGC_SW_PDN_REQ 0x0e4 + #define GPC_PU_PGC_SW_PUP_REQ 0x0f8 #define GPC_PU_PGC_SW_PDN_REQ 0x104 @@ -107,8 +132,30 @@ #define IMX8MN_OTG1_SW_Pxx_REQ BIT(2) #define IMX8MN_MIPI_SW_Pxx_REQ BIT(0) +#define IMX8MP_DDRMIX_Pxx_REQ BIT(19) +#define IMX8MP_MEDIA_ISP_DWP_Pxx_REQ BIT(18) +#define IMX8MP_HSIOMIX_Pxx_REQ BIT(17) +#define IMX8MP_MIPI_PHY2_Pxx_REQ BIT(16) +#define IMX8MP_HDMI_PHY_Pxx_REQ BIT(15) +#define IMX8MP_HDMIMIX_Pxx_REQ BIT(14) +#define IMX8MP_VPU_VC8K_Pxx_REQ BIT(13) +#define IMX8MP_VPU_G2_Pxx_REQ BIT(12) +#define IMX8MP_VPU_G1_Pxx_REQ BIT(11) +#define IMX8MP_MEDIMIX_Pxx_REQ BIT(10) +#define IMX8MP_GPU_3D_Pxx_REQ BIT(9) +#define IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ BIT(8) +#define IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ BIT(7) +#define IMX8MP_GPU_2D_Pxx_REQ BIT(6) +#define IMX8MP_AUDIOMIX_Pxx_REQ BIT(5) +#define IMX8MP_MLMIX_Pxx_REQ BIT(4) +#define IMX8MP_USB2_PHY_Pxx_REQ BIT(3) +#define IMX8MP_USB1_PHY_Pxx_REQ BIT(2) +#define IMX8MP_PCIE_PHY_SW_Pxx_REQ BIT(1) +#define IMX8MP_MIPI_PHY1_SW_Pxx_REQ BIT(0) + #define GPC_M4_PU_PDN_FLG 0x1bc +#define IMX8MP_GPC_PU_PWRHSK 0x190 #define GPC_PU_PWRHSK 0x1fc #define IMX8M_GPU_HSK_PWRDNACKN BIT(26) @@ -118,7 +165,6 @@ #define IMX8M_VPU_HSK_PWRDNREQN BIT(5) #define IMX8M_DISP_HSK_PWRDNREQN BIT(4) - #define IMX8MM_GPUMIX_HSK_PWRDNACKN BIT(29) #define IMX8MM_GPU_HSK_PWRDNACKN (BIT(27) | BIT(28)) #define IMX8MM_VPUMIX_HSK_PWRDNACKN BIT(26) @@ -137,6 +183,21 @@ #define IMX8MN_DISPMIX_HSK_PWRDNREQN BIT(7) #define IMX8MN_HSIO_HSK_PWRDNREQN BIT(5) +#define IMX8MP_MEDIAMIX_PWRDNACKN BIT(30) +#define IMX8MP_HDMIMIX_PWRDNACKN BIT(29) +#define IMX8MP_HSIOMIX_PWRDNACKN BIT(28) +#define IMX8MP_VPUMIX_PWRDNACKN BIT(26) +#define IMX8MP_GPUMIX_PWRDNACKN BIT(25) +#define IMX8MP_MLMIX_PWRDNACKN (BIT(23) | BIT(24)) +#define IMX8MP_AUDIOMIX_PWRDNACKN (BIT(20) | BIT(31)) +#define IMX8MP_MEDIAMIX_PWRDNREQN BIT(14) +#define IMX8MP_HDMIMIX_PWRDNREQN BIT(13) +#define IMX8MP_HSIOMIX_PWRDNREQN BIT(12) +#define IMX8MP_VPUMIX_PWRDNREQN BIT(10) +#define IMX8MP_GPUMIX_PWRDNREQN BIT(9) +#define IMX8MP_MLMIX_PWRDNREQN (BIT(7) | BIT(8)) +#define IMX8MP_AUDIOMIX_PWRDNREQN (BIT(4) | BIT(15)) + /* * The PGC offset values in Reference Manual * (Rev. 1, 01/2018 and the older ones) GPC chapter's @@ -179,6 +240,28 @@ #define IMX8MN_PGC_GPUMIX 23 #define IMX8MN_PGC_DISPMIX 26 +#define IMX8MP_PGC_NOC 9 +#define IMX8MP_PGC_MIPI1 12 +#define IMX8MP_PGC_PCIE 13 +#define IMX8MP_PGC_USB1 14 +#define IMX8MP_PGC_USB2 15 +#define IMX8MP_PGC_MLMIX 16 +#define IMX8MP_PGC_AUDIOMIX 17 +#define IMX8MP_PGC_GPU2D 18 +#define IMX8MP_PGC_GPUMIX 19 +#define IMX8MP_PGC_VPUMIX 20 +#define IMX8MP_PGC_GPU3D 21 +#define IMX8MP_PGC_MEDIAMIX 22 +#define IMX8MP_PGC_VPU_G1 23 +#define IMX8MP_PGC_VPU_G2 24 +#define IMX8MP_PGC_VPU_VC8000E 25 +#define IMX8MP_PGC_HDMIMIX 26 +#define IMX8MP_PGC_HDMI 27 +#define IMX8MP_PGC_MIPI2 28 +#define IMX8MP_PGC_HSIOMIX 29 +#define IMX8MP_PGC_MEDIA_ISP_DWP 30 +#define IMX8MP_PGC_DDRMIX 31 + #define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40) #define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc) @@ -212,6 +295,9 @@ struct imx_pgc_domain { const int voltage; const bool keep_clocks; struct device *dev; + + unsigned int pgc_sw_pup_reg; + unsigned int pgc_sw_pdn_reg; }; struct imx_pgc_domain_data { @@ -825,6 +911,303 @@ static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = { .pgc_regs = &imx7_pgc_regs, }; +static const struct imx_pgc_domain imx8mp_pgc_domains[] = { + [IMX8MP_POWER_DOMAIN_MIPI_PHY1] = { + .genpd = { + .name = "mipi-phy1", + }, + .bits = { + .pxx = IMX8MP_MIPI_PHY1_SW_Pxx_REQ, + .map = IMX8MP_MIPI_PHY1_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_MIPI1), + }, + + [IMX8MP_POWER_DOMAIN_PCIE_PHY] = { + .genpd = { + .name = "pcie-phy1", + }, + .bits = { + .pxx = IMX8MP_PCIE_PHY_SW_Pxx_REQ, + .map = IMX8MP_PCIE_PHY_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_PCIE), + }, + + [IMX8MP_POWER_DOMAIN_USB1_PHY] = { + .genpd = { + .name = "usb-otg1", + }, + .bits = { + .pxx = IMX8MP_USB1_PHY_Pxx_REQ, + .map = IMX8MP_USB1_PHY_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_USB1), + }, + + [IMX8MP_POWER_DOMAIN_USB2_PHY] = { + .genpd = { + .name = "usb-otg2", + }, + .bits = { + .pxx = IMX8MP_USB2_PHY_Pxx_REQ, + .map = IMX8MP_USB2_PHY_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_USB2), + }, + + [IMX8MP_POWER_DOMAIN_MLMIX] = { + .genpd = { + .name = "mlmix", + }, + .bits = { + .pxx = IMX8MP_MLMIX_Pxx_REQ, + .map = IMX8MP_MLMIX_A53_DOMAIN, + .hskreq = IMX8MP_MLMIX_PWRDNREQN, + .hskack = IMX8MP_MLMIX_PWRDNACKN, + }, + .pgc = BIT(IMX8MP_PGC_MLMIX), + .keep_clocks = true, + }, + + [IMX8MP_POWER_DOMAIN_AUDIOMIX] = { + .genpd = { + .name = "audiomix", + }, + .bits = { + .pxx = IMX8MP_AUDIOMIX_Pxx_REQ, + .map = IMX8MP_AUDIOMIX_A53_DOMAIN, + .hskreq = IMX8MP_AUDIOMIX_PWRDNREQN, + .hskack = IMX8MP_AUDIOMIX_PWRDNACKN, + }, + .pgc = BIT(IMX8MP_PGC_AUDIOMIX), + .keep_clocks = true, + }, + + [IMX8MP_POWER_DOMAIN_GPU2D] = { + .genpd = { + .name = "gpu2d", + }, + .bits = { + .pxx = IMX8MP_GPU_2D_Pxx_REQ, + .map = IMX8MP_GPU2D_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_GPU2D), + }, + + [IMX8MP_POWER_DOMAIN_GPUMIX] = { + .genpd = { + .name = "gpumix", + }, + .bits = { + .pxx = IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ, + .map = IMX8MP_GPUMIX_A53_DOMAIN, + .hskreq = IMX8MP_GPUMIX_PWRDNREQN, + .hskack = IMX8MP_GPUMIX_PWRDNACKN, + }, + .pgc = BIT(IMX8MP_PGC_GPUMIX), + .keep_clocks = true, + }, + + [IMX8MP_POWER_DOMAIN_VPUMIX] = { + .genpd = { + .name = "vpumix", + }, + .bits = { + .pxx = IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ, + .map = IMX8MP_VPUMIX_A53_DOMAIN, + .hskreq = IMX8MP_VPUMIX_PWRDNREQN, + .hskack = IMX8MP_VPUMIX_PWRDNACKN, + }, + .pgc = BIT(IMX8MP_PGC_VPUMIX), + .keep_clocks = true, + }, + + [IMX8MP_POWER_DOMAIN_GPU3D] = { + .genpd = { + .name = "gpu3d", + }, + .bits = { + .pxx = IMX8MP_GPU_3D_Pxx_REQ, + .map = IMX8MP_GPU3D_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_GPU3D), + }, + + [IMX8MP_POWER_DOMAIN_MEDIAMIX] = { + .genpd = { + .name = "mediamix", + }, + .bits = { + .pxx = IMX8MP_MEDIMIX_Pxx_REQ, + .map = IMX8MP_MEDIAMIX_A53_DOMAIN, + .hskreq = IMX8MP_MEDIAMIX_PWRDNREQN, + .hskack = IMX8MP_MEDIAMIX_PWRDNACKN, + }, + .pgc = BIT(IMX8MP_PGC_MEDIAMIX), + .keep_clocks = true, + }, + + [IMX8MP_POWER_DOMAIN_VPU_G1] = { + .genpd = { + .name = "vpu-g1", + }, + .bits = { + .pxx = IMX8MP_VPU_G1_Pxx_REQ, + .map = IMX8MP_VPU_G1_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_VPU_G1), + }, + + [IMX8MP_POWER_DOMAIN_VPU_G2] = { + .genpd = { + .name = "vpu-g2", + }, + .bits = { + .pxx = IMX8MP_VPU_G2_Pxx_REQ, + .map = IMX8MP_VPU_G2_A53_DOMAIN + }, + .pgc = BIT(IMX8MP_PGC_VPU_G2), + }, + + [IMX8MP_POWER_DOMAIN_VPU_VC8000E] = { + .genpd = { + .name = "vpu-h1", + }, + .bits = { + .pxx = IMX8MP_VPU_VC8K_Pxx_REQ, + .map = IMX8MP_VPU_VC8000E_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_VPU_VC8000E), + }, + + [IMX8MP_POWER_DOMAIN_HDMIMIX] = { + .genpd = { + .name = "hdmimix", + }, + .bits = { + .pxx = IMX8MP_HDMIMIX_Pxx_REQ, + .map = IMX8MP_HDMIMIX_A53_DOMAIN, + .hskreq = IMX8MP_HDMIMIX_PWRDNREQN, + .hskack = IMX8MP_HDMIMIX_PWRDNACKN, + }, + .pgc = BIT(IMX8MP_PGC_HDMIMIX), + .keep_clocks = true, + }, + + [IMX8MP_POWER_DOMAIN_HDMI_PHY] = { + .genpd = { + .name = "hdmi-phy", + }, + .bits = { + .pxx = IMX8MP_HDMI_PHY_Pxx_REQ, + .map = IMX8MP_HDMI_PHY_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_HDMI), + }, + + [IMX8MP_POWER_DOMAIN_MIPI_PHY2] = { + .genpd = { + .name = "mipi-phy2", + }, + .bits = { + .pxx = IMX8MP_MIPI_PHY2_Pxx_REQ, + .map = IMX8MP_MIPI_PHY2_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_MIPI2), + }, + + [IMX8MP_POWER_DOMAIN_HSIOMIX] = { + .genpd = { + .name = "hsiomix", + }, + .bits = { + .pxx = IMX8MP_HSIOMIX_Pxx_REQ, + .map = IMX8MP_HSIOMIX_A53_DOMAIN, + .hskreq = IMX8MP_HSIOMIX_PWRDNREQN, + .hskack = IMX8MP_HSIOMIX_PWRDNACKN, + }, + .pgc = BIT(IMX8MP_PGC_HSIOMIX), + .keep_clocks = true, + }, + + [IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP] = { + .genpd = { + .name = "mediamix-isp-dwp", + }, + .bits = { + .pxx = IMX8MP_MEDIA_ISP_DWP_Pxx_REQ, + .map = IMX8MP_MEDIA_ISPDWP_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_MEDIA_ISP_DWP), + }, +}; + +static const struct regmap_range imx8mp_yes_ranges[] = { + regmap_reg_range(GPC_LPCR_A_CORE_BSC, + IMX8MP_GPC_PGC_CPU_MAPPING), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_NOC), + GPC_PGC_SR(IMX8MP_PGC_NOC)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI1), + GPC_PGC_SR(IMX8MP_PGC_MIPI1)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_PCIE), + GPC_PGC_SR(IMX8MP_PGC_PCIE)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB1), + GPC_PGC_SR(IMX8MP_PGC_USB1)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB2), + GPC_PGC_SR(IMX8MP_PGC_USB2)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MLMIX), + GPC_PGC_SR(IMX8MP_PGC_MLMIX)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_AUDIOMIX), + GPC_PGC_SR(IMX8MP_PGC_AUDIOMIX)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU2D), + GPC_PGC_SR(IMX8MP_PGC_GPU2D)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPUMIX), + GPC_PGC_SR(IMX8MP_PGC_GPUMIX)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPUMIX), + GPC_PGC_SR(IMX8MP_PGC_VPUMIX)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU3D), + GPC_PGC_SR(IMX8MP_PGC_GPU3D)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIAMIX), + GPC_PGC_SR(IMX8MP_PGC_MEDIAMIX)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G1), + GPC_PGC_SR(IMX8MP_PGC_VPU_G1)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G2), + GPC_PGC_SR(IMX8MP_PGC_VPU_G2)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_VC8000E), + GPC_PGC_SR(IMX8MP_PGC_VPU_VC8000E)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMIMIX), + GPC_PGC_SR(IMX8MP_PGC_HDMIMIX)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMI), + GPC_PGC_SR(IMX8MP_PGC_HDMI)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI2), + GPC_PGC_SR(IMX8MP_PGC_MIPI2)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HSIOMIX), + GPC_PGC_SR(IMX8MP_PGC_HSIOMIX)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIA_ISP_DWP), + GPC_PGC_SR(IMX8MP_PGC_MEDIA_ISP_DWP)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_DDRMIX), + GPC_PGC_SR(IMX8MP_PGC_DDRMIX)), +}; + +static const struct regmap_access_table imx8mp_access_table = { + .yes_ranges = imx8mp_yes_ranges, + .n_yes_ranges = ARRAY_SIZE(imx8mp_yes_ranges), +}; + +static const struct imx_pgc_regs imx8mp_pgc_regs = { + .map = IMX8MP_GPC_PGC_CPU_MAPPING, + .pup = IMX8MP_GPC_PU_PGC_SW_PUP_REQ, + .pdn = IMX8MP_GPC_PU_PGC_SW_PDN_REQ, + .hsk = IMX8MP_GPC_PU_PWRHSK, +}; +static const struct imx_pgc_domain_data imx8mp_pgc_domain_data = { + .domains = imx8mp_pgc_domains, + .domains_num = ARRAY_SIZE(imx8mp_pgc_domains), + .reg_access_table = &imx8mp_access_table, + .pgc_regs = &imx8mp_pgc_regs, +}; + static const struct imx_pgc_domain imx8mn_pgc_domains[] = { [IMX8MN_POWER_DOMAIN_HSIOMIX] = { .genpd = { @@ -1120,6 +1503,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev) domain = pd_pdev->dev.platform_data; domain->regmap = regmap; domain->regs = domain_data->pgc_regs; + domain->genpd.power_on = imx_pgc_power_up; domain->genpd.power_off = imx_pgc_power_down; @@ -1141,6 +1525,7 @@ static const struct of_device_id imx_gpcv2_dt_ids[] = { { .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, }, { .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, }, { .compatible = "fsl,imx8mn-gpc", .data = &imx8mn_pgc_domain_data, }, + { .compatible = "fsl,imx8mp-gpc", .data = &imx8mp_pgc_domain_data, }, { .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, }, { } }; -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v4 4/5] arm64: dts: imx8mp: add GPC node with GPU power domains 2022-03-30 10:46 [PATCH v4 0/5] i.MX8MP GPC Lucas Stach ` (2 preceding siblings ...) 2022-03-30 10:46 ` [PATCH v4 3/5] soc: imx: gpcv2: add support for i.MX8MP power domains Lucas Stach @ 2022-03-30 10:46 ` Lucas Stach 2022-03-30 10:46 ` [PATCH v4 5/5] arm64: dts: imx8mp: add GPU nodes Lucas Stach 2022-03-31 8:13 ` [PATCH v4 0/5] i.MX8MP GPC Peng Fan 5 siblings, 0 replies; 11+ messages in thread From: Lucas Stach @ 2022-03-30 10:46 UTC (permalink / raw) To: Shawn Guo Cc: Pengutronix Kernel Team, NXP Linux Team, Rob Herring, Marek Vasut, Laurent Pinchart, Alexander Stein, Fabio Estevam, linux-arm-kernel, devicetree, patchwork-lst Add the power domains for the GPUs, which do not require any interaction with a blk-ctrl, but are simply two PU domains nested inside a MIX domain. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 41 +++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 6b840c05dd77..bd0c66e80e01 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/imx8mp-clock.h> +#include <dt-bindings/power/imx8mp-power.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -475,6 +476,46 @@ src: reset-controller@30390000 { interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; #reset-cells = <1>; }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mp-gpc"; + reg = <0x303a0000 0x1000>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_gpu2d: power-domain@6 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_GPU2D>; + clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>; + power-domains = <&pgc_gpumix>; + }; + + pgc_gpumix: power-domain@7 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_GPUMIX>; + clocks = <&clk IMX8MP_CLK_GPU_ROOT>, + <&clk IMX8MP_CLK_GPU_AHB>; + assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <800000000>, <400000000>; + }; + + pgc_gpu3d: power-domain@9 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_GPU3D>; + clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, + <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; + power-domains = <&pgc_gpumix>; + }; + }; + }; }; aips2: bus@30400000 { -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v4 5/5] arm64: dts: imx8mp: add GPU nodes 2022-03-30 10:46 [PATCH v4 0/5] i.MX8MP GPC Lucas Stach ` (3 preceding siblings ...) 2022-03-30 10:46 ` [PATCH v4 4/5] arm64: dts: imx8mp: add GPC node with GPU " Lucas Stach @ 2022-03-30 10:46 ` Lucas Stach 2022-03-31 8:13 ` [PATCH v4 0/5] i.MX8MP GPC Peng Fan 5 siblings, 0 replies; 11+ messages in thread From: Lucas Stach @ 2022-03-30 10:46 UTC (permalink / raw) To: Shawn Guo Cc: Pengutronix Kernel Team, NXP Linux Team, Rob Herring, Marek Vasut, Laurent Pinchart, Alexander Stein, Fabio Estevam, linux-arm-kernel, devicetree, patchwork-lst Add the DT nodes for both the 3D and 2D GPU cores found on the i.MX8MP. etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6204 etnaviv-gpu 38008000.gpu: model: GC520, revision: 5341 [drm] Initialized etnaviv 1.3.0 20151214 for etnaviv on minor 0 Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 31 +++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index bd0c66e80e01..24d710f5dc9b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -933,6 +933,37 @@ eqos: ethernet@30bf0000 { }; }; + gpu3d: gpu@38000000 { + compatible = "vivante,gc"; + reg = <0x38000000 0x8000>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, + <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, + <&clk IMX8MP_CLK_GPU_ROOT>, + <&clk IMX8MP_CLK_GPU_AHB>; + clock-names = "core", "shader", "bus", "reg"; + assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, + <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <800000000>, <800000000>; + power-domains = <&pgc_gpu3d>; + }; + + gpu2d: gpu@38008000 { + compatible = "vivante,gc"; + reg = <0x38008000 0x8000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, + <&clk IMX8MP_CLK_GPU_ROOT>, + <&clk IMX8MP_CLK_GPU_AHB>; + clock-names = "core", "bus", "reg"; + assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <800000000>; + power-domains = <&pgc_gpu2d>; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 11+ messages in thread
* RE: [PATCH v4 0/5] i.MX8MP GPC 2022-03-30 10:46 [PATCH v4 0/5] i.MX8MP GPC Lucas Stach ` (4 preceding siblings ...) 2022-03-30 10:46 ` [PATCH v4 5/5] arm64: dts: imx8mp: add GPU nodes Lucas Stach @ 2022-03-31 8:13 ` Peng Fan 2022-04-06 7:10 ` Peng Fan 5 siblings, 1 reply; 11+ messages in thread From: Peng Fan @ 2022-03-31 8:13 UTC (permalink / raw) To: Lucas Stach, Shawn Guo Cc: Pengutronix Kernel Team, dl-linux-imx, Rob Herring, Marek Vasut, Laurent Pinchart, Alexander Stein, Fabio Estevam, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, patchwork-lst@pengutronix.de > Subject: [PATCH v4 0/5] i.MX8MP GPC > > Hi Shawn, > > This is mostly a resend with all the reviews, acks and testing tags applied. I > dropped the HSIO blk-ctrl part from this series, as I noticed that this needs > some rework to better fit the upcoming HDMI blk-ctrl. The GPC part is still > complete, so the MEDIA blk-ctrl series from Laurent can be applied on top of > this v4. > > Regards, > Lucas Tested-by: Peng Fan <peng.fan@nxp.com> > > Lucas Stach (5): > soc: imx: gpcv2: add PGC control register indirection > dt-bindings: power: add defines for i.MX8MP power domain > soc: imx: gpcv2: add support for i.MX8MP power domains > arm64: dts: imx8mp: add GPC node with GPU power domains > arm64: dts: imx8mp: add GPU nodes > > .../bindings/power/fsl,imx-gpcv2.yaml | 2 + > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 72 +++ > drivers/soc/imx/gpcv2.c | 430 > +++++++++++++++++- > include/dt-bindings/power/imx8mp-power.h | 29 ++ > 4 files changed, 521 insertions(+), 12 deletions(-) create mode 100644 > include/dt-bindings/power/imx8mp-power.h > > -- > 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH v4 0/5] i.MX8MP GPC 2022-03-31 8:13 ` [PATCH v4 0/5] i.MX8MP GPC Peng Fan @ 2022-04-06 7:10 ` Peng Fan 2022-04-06 7:47 ` Lucas Stach 0 siblings, 1 reply; 11+ messages in thread From: Peng Fan @ 2022-04-06 7:10 UTC (permalink / raw) To: Lucas Stach, Shawn Guo Cc: Pengutronix Kernel Team, dl-linux-imx, Rob Herring, Marek Vasut, Laurent Pinchart, Alexander Stein, Fabio Estevam, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, patchwork-lst@pengutronix.de > Subject: RE: [PATCH v4 0/5] i.MX8MP GPC > > > Subject: [PATCH v4 0/5] i.MX8MP GPC > > > > Hi Shawn, > > > > This is mostly a resend with all the reviews, acks and testing tags > > applied. I dropped the HSIO blk-ctrl part from this series, as I > > noticed that this needs some rework to better fit the upcoming HDMI > > blk-ctrl. The GPC part is still complete, so the MEDIA blk-ctrl series > > from Laurent can be applied on top of this v4. > > > > Regards, > > Lucas > > Tested-by: Peng Fan <peng.fan@nxp.com> > > > > > Lucas Stach (5): > > soc: imx: gpcv2: add PGC control register indirection > > dt-bindings: power: add defines for i.MX8MP power domain > > soc: imx: gpcv2: add support for i.MX8MP power domains > > arm64: dts: imx8mp: add GPC node with GPU power domains > > arm64: dts: imx8mp: add GPU nodes Patch 2 is already in tree, but others still not. BTW: Do you have plan to resend the HSIO BLK CTRL from your V3 patchset? Laurent's V4 patchset also not apply now:) Regards, Peng. > > > > .../bindings/power/fsl,imx-gpcv2.yaml | 2 + > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 72 +++ > > drivers/soc/imx/gpcv2.c | 430 > > +++++++++++++++++- > > include/dt-bindings/power/imx8mp-power.h | 29 ++ > > 4 files changed, 521 insertions(+), 12 deletions(-) create mode > > 100644 include/dt-bindings/power/imx8mp-power.h > > > > -- > > 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v4 0/5] i.MX8MP GPC 2022-04-06 7:10 ` Peng Fan @ 2022-04-06 7:47 ` Lucas Stach 2022-04-06 8:28 ` Laurent Pinchart 0 siblings, 1 reply; 11+ messages in thread From: Lucas Stach @ 2022-04-06 7:47 UTC (permalink / raw) To: Peng Fan, Shawn Guo, Laurent Pinchart Cc: Pengutronix Kernel Team, dl-linux-imx, Rob Herring, Marek Vasut, Alexander Stein, Fabio Estevam, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, patchwork-lst@pengutronix.de Hi Peng, Am Mittwoch, dem 06.04.2022 um 07:10 +0000 schrieb Peng Fan: > > Subject: RE: [PATCH v4 0/5] i.MX8MP GPC > > > > > Subject: [PATCH v4 0/5] i.MX8MP GPC > > > > > > Hi Shawn, > > > > > > This is mostly a resend with all the reviews, acks and testing tags > > > applied. I dropped the HSIO blk-ctrl part from this series, as I > > > noticed that this needs some rework to better fit the upcoming HDMI > > > blk-ctrl. The GPC part is still complete, so the MEDIA blk-ctrl series > > > from Laurent can be applied on top of this v4. > > > > > > Regards, > > > Lucas > > > > Tested-by: Peng Fan <peng.fan@nxp.com> > > > > > > > > Lucas Stach (5): > > > soc: imx: gpcv2: add PGC control register indirection > > > dt-bindings: power: add defines for i.MX8MP power domain > > > soc: imx: gpcv2: add support for i.MX8MP power domains > > > arm64: dts: imx8mp: add GPC node with GPU power domains > > > arm64: dts: imx8mp: add GPU nodes > > Patch 2 is already in tree, but others still not. > > BTW: Do you have plan to resend the HSIO BLK CTRL from your V3 patchset? > Yes, I finally worked through all the issues in the HDMI subsystem and I'm ready to send out new HSIO + HDMI blk-ctrl patches today. > Laurent's V4 patchset also not apply now:) Right, I noticed this too. By dropping the HSIO DT patch from the series, the MEDIA series doesn't apply anymore. @Laurent: If you agree, I'll pick up your MEDIA blk-ctrl patches into my series, to make it easier for Shawn to apply the whole bunch. Regards, Lucas _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v4 0/5] i.MX8MP GPC 2022-04-06 7:47 ` Lucas Stach @ 2022-04-06 8:28 ` Laurent Pinchart 0 siblings, 0 replies; 11+ messages in thread From: Laurent Pinchart @ 2022-04-06 8:28 UTC (permalink / raw) To: Lucas Stach Cc: Peng Fan, Shawn Guo, Pengutronix Kernel Team, dl-linux-imx, Rob Herring, Marek Vasut, Alexander Stein, Fabio Estevam, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, patchwork-lst@pengutronix.de Hi Lucas, On Wed, Apr 06, 2022 at 09:47:28AM +0200, Lucas Stach wrote: > Am Mittwoch, dem 06.04.2022 um 07:10 +0000 schrieb Peng Fan: > > > Subject: RE: [PATCH v4 0/5] i.MX8MP GPC > > > > > > > Subject: [PATCH v4 0/5] i.MX8MP GPC > > > > > > > > Hi Shawn, > > > > > > > > This is mostly a resend with all the reviews, acks and testing tags > > > > applied. I dropped the HSIO blk-ctrl part from this series, as I > > > > noticed that this needs some rework to better fit the upcoming HDMI > > > > blk-ctrl. The GPC part is still complete, so the MEDIA blk-ctrl series > > > > from Laurent can be applied on top of this v4. > > > > > > > > Regards, > > > > Lucas > > > > > > Tested-by: Peng Fan <peng.fan@nxp.com> > > > > > > > Lucas Stach (5): > > > > soc: imx: gpcv2: add PGC control register indirection > > > > dt-bindings: power: add defines for i.MX8MP power domain > > > > soc: imx: gpcv2: add support for i.MX8MP power domains > > > > arm64: dts: imx8mp: add GPC node with GPU power domains > > > > arm64: dts: imx8mp: add GPU nodes > > > > Patch 2 is already in tree, but others still not. > > > > BTW: Do you have plan to resend the HSIO BLK CTRL from your V3 patchset? > > Yes, I finally worked through all the issues in the HDMI subsystem and > I'm ready to send out new HSIO + HDMI blk-ctrl patches today. > > > Laurent's V4 patchset also not apply now:) > > Right, I noticed this too. By dropping the HSIO DT patch from the > series, the MEDIA series doesn't apply anymore. > > @Laurent: If you agree, I'll pick up your MEDIA blk-ctrl patches into > my series, to make it easier for Shawn to apply the whole bunch. Whatever makes it more likely that the patches get merged in v5.19 is fine with me. Please do :-) -- Regards, Laurent Pinchart _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2022-04-08 13:27 UTC | newest] Thread overview: 11+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-03-30 10:46 [PATCH v4 0/5] i.MX8MP GPC Lucas Stach 2022-03-30 10:46 ` [PATCH v4 1/5] soc: imx: gpcv2: add PGC control register indirection Lucas Stach 2022-03-30 10:46 ` [PATCH v4 2/5] dt-bindings: power: add defines for i.MX8MP power domain Lucas Stach 2022-04-08 13:26 ` Shawn Guo 2022-03-30 10:46 ` [PATCH v4 3/5] soc: imx: gpcv2: add support for i.MX8MP power domains Lucas Stach 2022-03-30 10:46 ` [PATCH v4 4/5] arm64: dts: imx8mp: add GPC node with GPU " Lucas Stach 2022-03-30 10:46 ` [PATCH v4 5/5] arm64: dts: imx8mp: add GPU nodes Lucas Stach 2022-03-31 8:13 ` [PATCH v4 0/5] i.MX8MP GPC Peng Fan 2022-04-06 7:10 ` Peng Fan 2022-04-06 7:47 ` Lucas Stach 2022-04-06 8:28 ` Laurent Pinchart
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