From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0012CC433F5 for ; Tue, 26 Apr 2022 18:23:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=QkK7+eS+g3B9jvo4qI5ApfazFnAfUQV24rfE63Q2F5c=; b=2UOdeFQhJWyY25 OpVNQXQXO3zTdwoLqcimlaH7I7jSo01aUn/IHytMP8RDG8o17roHLNxz1VZcKSL1P8R1js6dnJ28q wwLLodVQAhaNLEydq4FbZ/eqqa8ZJVu3RRBk7sGgjf+nXnEUihAPramn5B70FcWlGPPtcarOZda5b rWWKXrSUI7iRDWHu7LGTz4/FekOk9N0XdSZc7FgIECkW9YcGQrddl57ddTet5PyzRm4ckotJ47qhw zw6VscyFsbpojIGr3HNGAtaebFwxw4MvMHwSijdy6WhJH2aZm0VV9rCOD27IsmDoCbwWH3NxFvxhx xaLjnuENqkDT93/2WLww==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1njPpS-00FfvQ-0W; Tue, 26 Apr 2022 18:22:26 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1njPm2-00FeVe-PP for linux-arm-kernel@lists.infradead.org; Tue, 26 Apr 2022 18:18:56 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 4627561768; Tue, 26 Apr 2022 18:18:54 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0738BC385AF; Tue, 26 Apr 2022 18:18:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1650997133; bh=efP2G0K8DrZDTGhQGB4Pi7LMFCmZUofC1OlYQ5CDdag=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=S11Yb+M8LJzruCSnklDiw0X9dqpbrPbmLBFJwfqi7ZZxMW9NTbcEuJ3MlhUO9Z3yG OmRK7Er9cPlct1GXYzolizHR7nfwZc7xk1rsNOCQIaIBCWTVqgbUB4cnz510WCHQem iTVknFBuVTc+c7rlW2WWsIGSJ6Qycss3kRS1MrOWXLz/f3K6tJpdI4ljgW7WPJui/K m+Nr7fudGhI+qKjZZzVoTHTGbSUic3DcOCV8I8ZglOXTZkB3TSBWg8AiioTsbQu5Ye +8W85da6kssYm7Yfj3oaMiDcIsHv9kICvj7+rmxx/RpiIOGgWFYBzjZsESF36csNWx MgQ8+sAEOwwmQ== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Marc Zyngier , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v5 06/12] arm64: Update name of ID_AA64ISAR0_EL1_ATOMIC to reflect ARM Date: Tue, 26 Apr 2022 19:16:58 +0100 Message-Id: <20220426181704.2583494-7-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220426181704.2583494-1-broonie@kernel.org> References: <20220426181704.2583494-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4087; h=from:subject; bh=efP2G0K8DrZDTGhQGB4Pi7LMFCmZUofC1OlYQ5CDdag=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBiaDcaf/0uOm9IA8j7h2sBjgBsBDp2Jk9imEJaGh4M Fi4KgBOJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYmg3GgAKCRAk1otyXVSH0JWFB/ 9IhhVhCimavC/Gs0QhBPWQPltAWeTfbtnXGgWRmCbQ9ggmi4NU7Lzh0addfB3WWNAgyrdA8jr8sucd Dd1omY0Y1pU+lqy+BuURcBzTQZD4dC1XJLs/c/k6QSlZfLEuwwPiS2t7/llYaosoS2VScQoSOO1fN4 GtCJzum8EO9UgZGO6Fxo2QmGdAVBuERe+jY0p+g83uXyXIS9zq9oyju27Jc7bu0zMKCW7uyycQVQNS oPxpthGVMQONdMUccgqaJHoVMPxDIFML2KzilZ8SCd8Q26i19B7U0biTSLSOrs17WZB43pNIMqVOEF 9qxr6UxFt2tvP6x89+pFummZBsf7Fi X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220426_111854_979586_5E5BF68F X-CRM114-Status: GOOD ( 16.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The architecture reference manual refers to the field in bits 23:20 of ID_AA64ISAR0_EL1 with the name "atomic" but the kernel defines for this bitfield use the name "atomics". Bring the two into sync to make it easier to cross reference with the specification. Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 2 +- arch/arm64/kernel/cpufeature.c | 6 +++--- arch/arm64/kvm/hyp/include/nvhe/fixed_config.h | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 331e2521a81a..0bb259ec6ee8 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -749,7 +749,7 @@ #define ID_AA64ISAR0_SM3_SHIFT 36 #define ID_AA64ISAR0_SHA3_SHIFT 32 #define ID_AA64ISAR0_RDM_SHIFT 28 -#define ID_AA64ISAR0_ATOMICS_SHIFT 20 +#define ID_AA64ISAR0_ATOMIC_SHIFT 20 #define ID_AA64ISAR0_CRC32_SHIFT 16 #define ID_AA64ISAR0_SHA2_SHIFT 12 #define ID_AA64ISAR0_SHA1_SHIFT 8 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index d72c4b4d389c..18833fe6d148 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -200,7 +200,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMIC_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), @@ -2013,7 +2013,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_SYSTEM_FEATURE, .matches = has_cpuid_feature, .sys_reg = SYS_ID_AA64ISAR0_EL1, - .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, + .field_pos = ID_AA64ISAR0_ATOMIC_SHIFT, .field_width = 4, .sign = FTR_UNSIGNED, .min_field_value = 2, @@ -2520,7 +2520,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), - HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), + HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMIC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h index 5ad626527d41..63a114b9b2ed 100644 --- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h +++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h @@ -163,7 +163,7 @@ ARM64_FEATURE_MASK(ID_AA64ISAR0_SHA1) | \ ARM64_FEATURE_MASK(ID_AA64ISAR0_SHA2) | \ ARM64_FEATURE_MASK(ID_AA64ISAR0_CRC32) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_ATOMICS) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR0_ATOMIC) | \ ARM64_FEATURE_MASK(ID_AA64ISAR0_RDM) | \ ARM64_FEATURE_MASK(ID_AA64ISAR0_SHA3) | \ ARM64_FEATURE_MASK(ID_AA64ISAR0_SM3) | \ -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel