From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B6FA5C433EF for ; Tue, 3 May 2022 17:04:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=Aq0l00gx4t357xY7xCkfGvi3VrLienevPY9X+fP8rfw=; b=nRW7OWBXHbnVfm 2USq4jjd5CxeddueRbL1eRalKnf5JHDH7QPTdJv7WwUMWK7YzCIoSLsOskUymCwPWE3eh8ZTsIfFB QRhfTEJ/TrOU7Qr+oX3OZvGpSqjjWsgStWclqWXZwjZvuYnZDaCJxPvrLPGI+DJEPEVUKnhT602QT M5yc14++cPvpDUTb7YT/2q3oIIyFBqublcNQ63Aql0ADkp+ZUVzwru7JUwH6wkQcXZ8gi2keiCaF3 STuglp8wB4l9sAbN4gTfGn3SXyH/sZNX474EptXqhl6z71ERp7Z+VD6F/VOc21ZUQb3IX4RZ+UXp9 +BUsf1WuSmLMiOSo9F1A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nlvvh-006saz-AC; Tue, 03 May 2022 17:03:17 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nlvvc-006sXy-3Y for linux-arm-kernel@lists.infradead.org; Tue, 03 May 2022 17:03:14 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 5D140B81F30; Tue, 3 May 2022 17:03:10 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B1F3BC385A4; Tue, 3 May 2022 17:03:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1651597388; bh=PKzBShZuRiyJWXAVYwORa+FSj+6F4IG4y7q0G4TED/o=; h=From:To:Cc:Subject:Date:From; b=Of9nyGGvfHfeoURNr3SxVbi/3fwgSFKzALPYT4vI6E/cfoJg11CBx1Bcmc4mKBcUH lSbNpkwZt6ymYZsExmdj67wkoB1BCHI0lxxqHW81LffY2yNTQsI6+pSXa3mEN7A8F3 A5TuCcwjhkRNiKCx0n7Iij90dRr7tA0Kf+Au/0yEiV/mWxnSB6zh/0Wr/TslJF/93D j9vdE8uwaaa1DnqpqORO3uEJir8rc2iLHuYTUT8OOASYFU6ZmLk2p1EGXc++oLlahB 4qvrQh8vNFtMIi54o/eyTE9pIf5U7KjSw9KPlVPznuXYFxqLKEY1enu5dLT6LXpzCk GyxSeDjA+2jCA== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Marc Zyngier , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v6 00/12] arm64: Automatic system register definition generation Date: Tue, 3 May 2022 18:02:21 +0100 Message-Id: <20220503170233.507788-1-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6500; h=from:subject; bh=PKzBShZuRiyJWXAVYwORa+FSj+6F4IG4y7q0G4TED/o=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBicWAeriW2Do5msVuvkWV4M88+iXshZr73pxIGj+WC mgsog9aJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYnFgHgAKCRAk1otyXVSH0F/TB/ 9cCHzNyKw7D//gGWcH5BasV1hn/XX1BDCpRKnF+jgN7qnn9hRn2XZ+aYOjkQuk6NZdW9NMrscu8u/U 92E+JbpYr/N2QyKeRxmzbHfn16Vgz+ArtrjcCvYR9JqqMSTacGLakZb6UpY+zFVO7p6+18DcErGmL+ PQ04t127PK/8stdWk2Jz4bQOvPM62clywmW/GMETkT1SO0gAaC6CfBcUOqdWMiRm9feUlguV92mooV ZbbWZDKWT1D/R5b90l8fBMKn+pilLFxoETlN+UGKNTydOnuw35uDEP37bJ7tE32fFHxMsyq7lHi66P b0d/3eC/FHe0NT3GHe2TnAGiXXGiEc X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220503_100313_226486_4493B9A3 X-CRM114-Status: GOOD ( 25.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The arm64 kernel requires some metadata for each system register it may need to access. Currently we have: * A SYS_ definition which sorresponds to a sys_reg() macro. This is used both to look up a sysreg by encoding (e.g. in KVM), and also to generate code to access a sysreg where the assembler is unaware of the specific sysreg encoding. Where assemblers support the S3__C_C_ syntax for system registers, we could use this rather than manually assembling the instructions. However, we don't have consistent definitions for these and we currently still need to handle toolchains that lack this feature. * A set of __SHIFT and __MASK definitions, which can be used to extract fields from the register, or to construct a register from a set of fields. These do not follow the convention used by , and the masks are not shifted into place, preventing their use in FIELD_PREP() and FIELD_GET(). We require the SHIFT definitions for inline assembly (and WIDTH definitions would be helpful for UBFX/SBFX), so we cannot only define a shifted MASK. Defining a SHIFT, WIDTH, shifted MASK and unshifted MASK is tedious and error-prone and life is much easier when they can be relied up to exist when writing code. * A set of __ definitions for each enumerated value a field may hold. These are used when identifying the presence of features. Atop of this, other code has to build up metadata at runtime (e.g. the sets of RES0/RES1 bits in a register). This patch series introduces a script which describes registers and the fields within them in a format that is easy to cross reference with the architecture reference manual and uses them to generate the constants we use in a standard format: | #define REG_ID_AA64ISAR0_EL1 S3_0_C0_C6_0 | #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) | #define SYS_ID_AA64ISAR0_EL1_Op0 3 | #define SYS_ID_AA64ISAR0_EL1_Op1 0 | #define SYS_ID_AA64ISAR0_EL1_CRn 0 | #define SYS_ID_AA64ISAR0_EL1_CRm 6 | #define SYS_ID_AA64ISAR0_EL1_Op2 0 | #define ID_AA64ISAR0_EL1_RNDR GENMASK(63, 60) | #define ID_AA64ISAR0_EL1_RNDR_MASK GENMASK(63, 60) | #define ID_AA64ISAR0_EL1_RNDR_SHIFT 60 | #define ID_AA64ISAR0_EL1_RNDR_WIDTH 4 | #define ID_AA64ISAR0_EL1_RNDR_NI UL(0b0000) | #define ID_AA64ISAR0_EL1_RNDR_IMP UL(0b0001) This should be particularly useful for the ID registers where we will be able to specify just the register and field for more of the bitfield information, simplifying ARM64_FTR_BITS() and providing helpers for use in struct arm64_cpu_capabilities or for hwcaps. For registers which have shared definitions (eg, registers that have versions with identical layouts at multiple ELs) we support defining a shared layout for those registers which is then referenced from the per register definition. At the moment this is only intended to express metadata from the architecture, and does not handle policy imposed by the kernel, such as values exposed to userspace or VMs. In future this could be extended to express such information. This could also be extended to cover more information such as the FTR_SIGNED/FTR_UNSIGNED distinction. There is also currently no support for registers which change layout at runtime, for example based on virtualisation settings - these could be manually handled for the time being, or the script extended. Rather than attempting to convert every register at once the current series converts a few sample registers to provide some concrete examples but allow for easier updating during review of the file format and the script. Handling a register at a time should also make review less taxing so it seems like a sensible approach in general. The generation script was originally written by Mark Rutland and subsequently improved and integrated into the kernel build by me. v6: - Don't generate intermediate defines for individual RES0/1 bitfields, just emit GENMASK()s directly into the overall RES0/1 defines for the register. v5: - Introduce and use SYS_FIELD_PREP() and SYS_FIELD_PREP_ENUM(). - Use helper macros for SCTLR_ELx.TCF as well as TCF0. - Rename sysreg-gen.h to sysreg-defs.h. - Use UL rather than ULL. - Implement a SharedLayout statement, currently as a noop. - Fix checks to ensure regexps only match in the correct block in the script. - Minor stylistic tweaks. v4: - Rebase onto v5.18-rc3. v3: - Rebase onto v5.18-rc1. v2: - Fix issue with building bounds.s in an O= build by renaming the generated header. Mark Brown (11): arm64/sysreg: Introduce helpers for access to sysreg fields arm64/mte: Make TCF0 naming and field values more standard arm64/mte: Make TCF field values and naming more standard arm64/sysreg: Rename SCTLR_EL1_NTWE/TWI to SCTLR_EL1_nTWE/TWI arm64/sysreg: Define bits for previously RES1 fields in SCTLR_EL1 arm64: Update name of ID_AA64ISAR0_EL1_ATOMIC to reflect ARM arm64/sysreg: Standardise ID_AA64ISAR0_EL1 macro names arm64/sysreg: Enable automatic generation of system register definitions arm64/sysreg: Generate definitions for ID_AA64ISAR0_EL1 arm64/sysreg: Generate definitions for TTBRn_EL1 arm64/sysreg: Generate definitions for SCTLR_EL1 Mark Rutland (1): arm64: Add sysreg header generation scripting arch/arm64/include/asm/Kbuild | 1 + arch/arm64/include/asm/archrandom.h | 2 +- arch/arm64/include/asm/sysreg.h | 117 +++----- arch/arm64/kernel/cpufeature.c | 70 ++--- arch/arm64/kernel/mte.c | 15 +- .../arm64/kvm/hyp/include/nvhe/fixed_config.h | 28 +- arch/arm64/mm/fault.c | 3 +- arch/arm64/tools/Makefile | 8 +- arch/arm64/tools/gen-sysreg.awk | 261 ++++++++++++++++++ arch/arm64/tools/sysreg | 200 ++++++++++++++ 10 files changed, 570 insertions(+), 135 deletions(-) create mode 100755 arch/arm64/tools/gen-sysreg.awk create mode 100644 arch/arm64/tools/sysreg base-commit: b2d229d4ddb17db541098b83524d901257e93845 -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel