From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8DF4DC433EF for ; Tue, 3 May 2022 17:05:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=CoGquciZYWbbkqm2Sx+B0YKpwvhUwiyMcbJEXwX8wto=; b=Ry1HAfJ0ZJTyl6 jrU52hnSdGcZE//4toGjA94e5mMHz4KU5caAH6NOFgsxM9tm85pZ/JMEGzoTrxl3udPBKLkBWa8o1 hF6PWjSidLJ905nnQfyrEW7nhVrDY4ocMkkeNcLAz27vhZvXvf5gIPvscsfk4ROmo4JBuoxsAu/8k D0cxRFUHQu6XdIyQB0QKp7jAnmqKkAhHPCenbNiRlK30uWhs5wsT4Tsav+CN4odtC06oZyo0e8d9U x96GhPoIA2UZqTPwEVzxYY4Pz+KysvD49mo3FQUs4SVL1QHNtK2g0VKmZBaAxME1xiZ7sHCV0kAPV tSkqHfGJ1GDamzGVqVxg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nlvwY-006tAF-5V; Tue, 03 May 2022 17:04:10 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nlvvh-006sb9-40 for linux-arm-kernel@lists.infradead.org; Tue, 03 May 2022 17:03:18 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 784A7616C7; Tue, 3 May 2022 17:03:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4E370C385B3; Tue, 3 May 2022 17:03:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1651597395; bh=6pN5UpVWlleiePKC12bEbEwloGqGAfXRPitx4GQuuKQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=c2eYHSyUpRvoi7FS9+p324iMu75Ro8CeVQVXKxEy56Djzls538WmO7eeX/zdhQH84 QNum/HLWSMaXQVI/IwGaKEKMy+tErLu8mukpZPcf8uUqaYJbSMbv5Ye5FIn5pUc6lz Ue0ZE+VRkEfUKowWb4qo/fS3xOk7w5xaNSaOnIut674bAWutlLrgx3hG6eXX6KdYEe GmRg423c8Ahq1Spx1bBE0uOmxFCgVeIaKq2C+ZVkf7g+PrP0xUBY8b6hjPDphJ7+u0 P8+9kzlzhqougNV23azm/0TKg5Fr4EeviAA3bsKNTnT6FvM2NkA2Ni/M9Hmi3ng/mf mwpLYsTBytp1g== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Marc Zyngier , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v6 03/12] arm64/mte: Make TCF field values and naming more standard Date: Tue, 3 May 2022 18:02:24 +0100 Message-Id: <20220503170233.507788-4-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220503170233.507788-1-broonie@kernel.org> References: <20220503170233.507788-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4002; h=from:subject; bh=6pN5UpVWlleiePKC12bEbEwloGqGAfXRPitx4GQuuKQ=; b=owGbwMvMwMWocq27KDak/QLjabUkhqTCBIWN+n4SlbzJF5d4HAz3WBhV8vyNmHvVP6GT85J4ja6d cjrcyWjMwsDIxSArpsiy9lnGqvRwia3zH81/BTOIlQlkCgMXpwBMRKiB/Z9SWQin9atgjd833wvX/m viLJMJ9Y1+ILPMqkeW/3wd0yVPySn1HBfKJctrFL0k6q//9n6zqzB/84bv7D97zudODFI+6SGhylH2 3j/JtrSlq4uvOEhU1fulDDPH59CPf1J6Eu7bVmyc9yH5Ep/V00c/Xp1X0rbN/i0REqeU+M3S80Fawo St5fs2cvo/Ct56sEXoxSLXZHN31++s4h27FfIF1hdfD2EIX7hXvWJXSbjShPdSHg++yKYHfzy9rGJ3 JfecV8t+Ne3XUFD8sMJtrdZi/mNPz2WenuQg3RrXFMRi981lyvs3Wzs1+4Ii/wvUn13So9MnI98g/j zBPoaXJ3xlxp7eS5x+J7cHb1gJAA== X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220503_100317_334472_AD109B86 X-CRM114-Status: GOOD ( 17.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In preparation for automatic generation of the defines for system registers make the values used for the enumeration in SCTLR_ELx.TCF suitable for use with the newly defined SYS_FIELD_PREP_ENUM helper, removing the shift from the define and using the helper to generate it on use instead. Since we only ever interact with this field in EL1 and in preparation for generation of the defines also rename from SCTLR_ELx to SCTLR_EL1. SCTLR_EL2 is not quite the same as SCTLR_EL1 so the conversion does not share the field definitions. There should be no functional change from this patch. Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 14 +++++++------- arch/arm64/kernel/mte.c | 9 +++++---- arch/arm64/mm/fault.c | 3 ++- 3 files changed, 14 insertions(+), 12 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 6dc840be0268..732d84111d9f 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -631,13 +631,6 @@ #define SCTLR_ELx_DSSBS (BIT(44)) #define SCTLR_ELx_ATA (BIT(43)) -#define SCTLR_ELx_TCF_SHIFT 40 -#define SCTLR_ELx_TCF_NONE (UL(0x0) << SCTLR_ELx_TCF_SHIFT) -#define SCTLR_ELx_TCF_SYNC (UL(0x1) << SCTLR_ELx_TCF_SHIFT) -#define SCTLR_ELx_TCF_ASYNC (UL(0x2) << SCTLR_ELx_TCF_SHIFT) -#define SCTLR_ELx_TCF_ASYMM (UL(0x3) << SCTLR_ELx_TCF_SHIFT) -#define SCTLR_ELx_TCF_MASK (UL(0x3) << SCTLR_ELx_TCF_SHIFT) - #define SCTLR_ELx_ENIA_SHIFT 31 #define SCTLR_ELx_ITFSB (BIT(37)) @@ -677,6 +670,13 @@ #define SCTLR_EL1_EPAN (BIT(57)) #define SCTLR_EL1_ATA0 (BIT(42)) +#define SCTLR_EL1_TCF_SHIFT 40 +#define SCTLR_EL1_TCF_NONE (UL(0x0)) +#define SCTLR_EL1_TCF_SYNC (UL(0x1)) +#define SCTLR_EL1_TCF_ASYNC (UL(0x2)) +#define SCTLR_EL1_TCF_ASYMM (UL(0x3)) +#define SCTLR_EL1_TCF_MASK (UL(0x3) << SCTLR_EL1_TCF_SHIFT) + #define SCTLR_EL1_TCF0_SHIFT 38 #define SCTLR_EL1_TCF0_NONE (UL(0x0)) #define SCTLR_EL1_TCF0_SYNC (UL(0x1)) diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c index 41469b69a48e..98f5e1e13c36 100644 --- a/arch/arm64/kernel/mte.c +++ b/arch/arm64/kernel/mte.c @@ -106,7 +106,8 @@ int memcmp_pages(struct page *page1, struct page *page2) static inline void __mte_enable_kernel(const char *mode, unsigned long tcf) { /* Enable MTE Sync Mode for EL1. */ - sysreg_clear_set(sctlr_el1, SCTLR_ELx_TCF_MASK, tcf); + sysreg_clear_set(sctlr_el1, SCTLR_EL1_TCF_MASK, + SYS_FIELD_PREP(SCTLR_EL1, TCF, tcf)); isb(); pr_info_once("MTE: enabled in %s mode at EL1\n", mode); @@ -122,12 +123,12 @@ void mte_enable_kernel_sync(void) WARN_ONCE(system_uses_mte_async_or_asymm_mode(), "MTE async mode enabled system wide!"); - __mte_enable_kernel("synchronous", SCTLR_ELx_TCF_SYNC); + __mte_enable_kernel("synchronous", SCTLR_EL1_TCF_SYNC); } void mte_enable_kernel_async(void) { - __mte_enable_kernel("asynchronous", SCTLR_ELx_TCF_ASYNC); + __mte_enable_kernel("asynchronous", SCTLR_EL1_TCF_ASYNC); /* * MTE async mode is set system wide by the first PE that @@ -144,7 +145,7 @@ void mte_enable_kernel_async(void) void mte_enable_kernel_asymm(void) { if (cpus_have_cap(ARM64_MTE_ASYMM)) { - __mte_enable_kernel("asymmetric", SCTLR_ELx_TCF_ASYMM); + __mte_enable_kernel("asymmetric", SCTLR_EL1_TCF_ASYMM); /* * MTE asymm mode behaves as async mode for store diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 77341b160aca..5e280cc566ca 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -335,7 +335,8 @@ static void do_tag_recovery(unsigned long addr, unsigned int esr, * It will be done lazily on the other CPUs when they will hit a * tag fault. */ - sysreg_clear_set(sctlr_el1, SCTLR_ELx_TCF_MASK, SCTLR_ELx_TCF_NONE); + sysreg_clear_set(sctlr_el1, SCTLR_EL1_TCF_MASK, + SYS_FIELD_PREP_ENUM(SCTLR_EL1, TCF, NONE)); isb(); } -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel