From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9DA59C433EF for ; Sat, 7 May 2022 14:12:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9gNOoIsIrUOUppFAfIOuA7qLBVAHC4EfAmdqwyoB/2Y=; b=oe7aBj+8bj/uMz fPBn3G5Eg1J70oPDRfpB0D464n5uLdSfSLNs8/aDh2BY0Bhfi1D3eDsdVMc7uGAaEIgB2OQeJiXlN tfxOiE8H5r2VcLpkZjzzdRU+g9RxkK1y4UP8qpBrsK5o5UPhau0/L5MmAse5IEBk5TFOIaBrBf605 2nudO2WU4vJclRILGo3LTPh528tRhoCl+zNyFZ/sp6BBROhDKNGN0Lk30cc5bdWpVkhcBFzjXafQ9 0ph8OKAcjRgko2cpuisVrmRfDGOj+laNZunWOG/B+eWKuj+cQxY1543olfKz9ap1/P0pt2Z/VkuhL pcAG+4buQZ8dkxyPNfKA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nnL9O-007Mos-Oc; Sat, 07 May 2022 14:11:14 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nnL9L-007MoN-F3 for linux-arm-kernel@lists.infradead.org; Sat, 07 May 2022 14:11:12 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 6F25861234; Sat, 7 May 2022 14:11:09 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B80BDC385A5; Sat, 7 May 2022 14:11:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1651932668; bh=yYbW1VYEkBgjUdJEWnHpf9fQF+9II7U7hTlVk4opQww=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=DZaQZ602znpG9kKXvb6U3e1b76WAn84ZMPGk96M+A8YTLWZfwQBTKM2VzF34a5NPm xE8ZgFMZebGSGTtzARm52yrtc7RkcYtqGaNKXHedPnnk0nJDxmSQaZf1+us2w7bRRW 3Q2mUyUlOo/bZ0BirakaLJ4rvo8KwBdhrbVSl/tkSvOmOx1N2+SOd521O2mGqfq86o 2xS9EavlzWbQ9gji/Z5aM+a/4i0UYTbHVlG9ufFKWIDAJdSRYEihs5iOtiqsk0Bov/ E+T/dWiQxLA3pxWNEW8ccSIjTpNa9SvsB6NP39eP8MgZzCxooXsreTa+krPwBUqrkG NZtajDqUQzZ7Q== Date: Sat, 7 May 2022 15:19:35 +0100 From: Jonathan Cameron To: Yannick Brosseau Cc: lars@metafoo.de, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, fabrice.gasnier@foss.st.com, olivier.moysan@foss.st.com, paul@crapouillou.net, linux-iio@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] iio: adc: stm32: Fix check for spurious IRQs on STM32F4 Message-ID: <20220507151935.3d3fa270@jic23-huawei> In-Reply-To: <20220506225617.1774604-3-yannick.brosseau@gmail.com> References: <20220506225617.1774604-1-yannick.brosseau@gmail.com> <20220506225617.1774604-3-yannick.brosseau@gmail.com> X-Mailer: Claws Mail 4.1.0 (GTK 3.24.33; x86_64-pc-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220507_071111_639440_DABCCC2A X-CRM114-Status: GOOD ( 24.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 6 May 2022 18:56:17 -0400 Yannick Brosseau wrote: > The check for spurious IRQs introduced in 695e2f5c289bb assumed that the bits > in the control and status registers are aligned. This is true for the H7 and MP1 > version, but not the F4. > > Instead of comparing both registers bitwise, we check the bit in the status and control > for each interrupt we are interested in. > > Signed-off-by: Yannick Brosseau I don't entirely follow the flow here, so will be relying on the driver maintainers for feedback on this one (even more than normal!) One question inline. Jonathan > --- > drivers/iio/adc/stm32-adc.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c > index a68ecbda6480..5b0f138333ee 100644 > --- a/drivers/iio/adc/stm32-adc.c > +++ b/drivers/iio/adc/stm32-adc.c > @@ -1422,9 +1422,10 @@ static irqreturn_t stm32_adc_threaded_isr(int irq, void *data) > return IRQ_HANDLED; > } > > - if (!(status & mask)) > + if(!((status & regs->isr_eoc.mask) && (mask & regs->ier_eoc.mask)) || > + ((status & regs->isr_ovr.mask) && (mask & regs->ier_ovr.mask))) For this second condition if it is true, have we not already entered the previous if (status & regs->isr_ovr.mask) and hence never reached this check? There is a comment above that to say if we get there over mask should already be disable. If that's not true for some reason then we should also adjust that check and the comment. Or perhaps I'm getting confused by the bracketing and operator precedence. Should this not be... > + if(!(((status & regs->isr_eoc.mask) && (mask & regs->ier_eoc.mask)) || > + ((status & regs->isr_ovr.mask) && (mask & regs->ier_ovr.mask)))) ? So as to be the equivalent of the !(status & mask) just checking bits separately. > dev_err_ratelimited(&indio_dev->dev, > - "Unexpected IRQ: IER=0x%08x, ISR=0x%08x\n", > + "Unexpected IRQ: CR1/IER=0x%08x, SR/ISR=0x%08x\n", > mask, status); > > return IRQ_NONE; > @@ -1438,7 +1439,9 @@ static irqreturn_t stm32_adc_isr(int irq, void *data) > u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); > u32 mask = stm32_adc_readl(adc, regs->ier_eoc.reg); > > - if (!(status & mask)) > + /* Check that we have the interrupt we care about are enabled and active */ > + if(!((status & regs->isr_eoc.mask) && (mask & regs->ier_eoc.mask)) || > + ((status & regs->isr_ovr.mask) && (mask & regs->ier_ovr.mask))) > return IRQ_WAKE_THREAD; > > if (status & regs->isr_ovr.mask) { _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel