From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B8FC0C433F5 for ; Tue, 10 May 2022 16:13:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=R/0r1UlRtrIyvWu43yzIEVyHF8QhqnezO4d/yuaX/BI=; b=WV38Zfs5lPiNvp Q2Puoteau9cmkP9RTWUvd65uiUAa3c+IlFn86FCcXV0/I4LPHraW+eVT1pops3O2sBp+sN+ZnwlIh TUJDvI3HOacjn4ZPQ8Xe9+FTSP28siCEsi0n621mXuExoFAk0sdhXo9I+0GmlxamffVwqf0PY7sTK 6z3PCml8PtVHjCCHVGGvk1QE1LjYv3yzA8mdUBmZ2xsMZ2WZtxZ7wuOq/nwW6NjpIA8smO9rtoG+o ///ixkXLDWw9B+Zo82DGKuxzH97Kd33pS3U21INtPjoCrpl1O5EgePSI6o5BhNh5nCQkrCA2M3b6x B2SftWCDW4nTKndQh/Fw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1noSTY-002xa5-KO; Tue, 10 May 2022 16:12:40 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1noSTN-002xU0-Fr for linux-arm-kernel@lists.infradead.org; Tue, 10 May 2022 16:12:30 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 3E404617B4; Tue, 10 May 2022 16:12:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 376A6C385CC; Tue, 10 May 2022 16:12:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652199147; bh=RTB8/lu5EO1sNW4d2TIMGS9eN5tEVsdAg8rP13UNo8w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o1FScKQCkh8/lKzkvvmPHrcuGQs19ahTA/Eg1ZbUKUuyt+qfY52EZGF3rH37BP7tm 2QIm2XfWWIMuCShCxLfWp6dbs6WVA6pMxkbeWH7QsE5q3jj0qrfupXY0GS2hitIcjO qTnNSwQY4hqRHvZhQyHbuFhbuY5L3L0rz/UHrf0IFywnj6N5X4/vla+KNRzNJuMnuf Mezl6Twx+ud0Ky8Y7gTGUQkqiC8ZH98Ba5mnyaqc2td8ZfBLfT5raTNAwOrP9FXoMo SELjI2AztWsvMF7zPioJoZ0gUKJSbcFLM60E7shINq0qxj7EC7p7aDV6qdcICVwIQW ue0WiNSHn2p+Q== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Marc Zyngier , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v1 01/12] arm64/fp: Make SVE and SME length register definition match architecture Date: Tue, 10 May 2022 17:11:57 +0100 Message-Id: <20220510161208.631259-2-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220510161208.631259-1-broonie@kernel.org> References: <20220510161208.631259-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2178; h=from:subject; bh=RTB8/lu5EO1sNW4d2TIMGS9eN5tEVsdAg8rP13UNo8w=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBieo7NgdJNPyWOe2nZuZ8Vx+PavIPTTJADfpHSMwLt RVMJoiuJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYnqOzQAKCRAk1otyXVSH0FpWB/ 0R+0hLQEoIA/AtDynOD2hBEorSCyOSKnC2NEDsIsey340jlRKPRisRfNJVXPsugNlvzl/1FxhkT84j dkaNk4mLmJ/ADhQX+2Aay6XuJnCjQ/mNgz1/pXvE4e2/d7mcCuRLDkPj+fvkDun3CcGyvwgArTjGB7 zzyZf7XJqMXmhiVf/0s1nIe9Fejmi5WAo1Kvff7MLnoh7bXk4WpkMlbv/EkGpyBRk4d1oqm9Bv1AEx RtHsX1J2UdJ2zasIktGK5REWUcWT82s6hflODTTrTI+NZmlPEUVyBWbyI72wmcqhgCEIaDtNN+qHNK ELl8mIcz83IKs+97wiHtzu2HUsBcQt X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220510_091229_665844_B24610AF X-CRM114-Status: GOOD ( 15.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently (as of DDI0487H.a) the architecture defines the vector length control field in ZCR and SMCR as being 4 bits wide with an additional 5 bits reserved above it marked as RAZ/WI for future expansion. The kernel currently attempts to anticipate such expansion by treating these extra bits as part of the LEN field but this will be inconvenient when we start generating the defines and would cause problems in the event that the architecture goes a different direction with these fields. Let's instead change the defines to reflect the currently defined architecture, we can update in future as needed. No change in behaviour should be seen in any system, even emulated systems using the maximum allowed vector length for the current architecture. Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 422741ca5631..4d78b6aeebb4 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -1113,26 +1113,16 @@ #define DCZID_DZP_SHIFT 4 #define DCZID_BS_SHIFT 0 -/* - * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which - * are reserved by the SVE architecture for future expansion of the LEN - * field, with compatible semantics. - */ #define ZCR_ELx_LEN_SHIFT 0 -#define ZCR_ELx_LEN_SIZE 9 -#define ZCR_ELx_LEN_MASK 0x1ff +#define ZCR_ELx_LEN_SIZE 4 +#define ZCR_ELx_LEN_MASK 0xf #define SMCR_ELx_FA64_SHIFT 31 #define SMCR_ELx_FA64_MASK (1 << SMCR_ELx_FA64_SHIFT) -/* - * The SMCR_ELx_LEN_* definitions intentionally include bits [8:4] which - * are reserved by the SME architecture for future expansion of the LEN - * field, with compatible semantics. - */ #define SMCR_ELx_LEN_SHIFT 0 -#define SMCR_ELx_LEN_SIZE 9 -#define SMCR_ELx_LEN_MASK 0x1ff +#define SMCR_ELx_LEN_SIZE 4 +#define SMCR_ELx_LEN_MASK 0xf #define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */ #define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */ -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel