From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3729FC433EF for ; Thu, 12 May 2022 19:07:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Message-ID: Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:References: List-Owner; bh=XhTQ5WGLNpq7zfmrj2NBDItLlfz63a33TjMQ3nSMY+w=; b=b04kbyFoEGyVdP qjarg2beRBAHEqU7iJd9X2I5HhbJflbqQPH+x2JEZ396Zxu65gj3LZ4vIKKUretPTYYutWKi/QnFv 0//KFmE5Ta+REp9+X53XDD11GePHHo3/+R775LeXo3eEPSYp1bzdfr65CPf+SVgZqzHzkUhzIy0bz /rnTXHFaLJvS/YcWGd9hCwuG9YbnJ9L7HGjsTo0aSQ5Gn/m1GWXI2GXM7e9Mm73AOZy8tz6dFNqJ5 4R7QVvniPaCMFzKMdIXye5uebfzGAXEjLVWmz+06KtWjl00OdSvvHSC7avAME+VVHmIlMJCETAOZm 7cPaN68GIPykDnnV/SCg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1npE8w-00DCrq-7k; Thu, 12 May 2022 19:06:34 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1npE8s-00DCrP-Ly for linux-arm-kernel@lists.infradead.org; Thu, 12 May 2022 19:06:32 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 6ECDB61B89; Thu, 12 May 2022 19:06:29 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8DC36C385B8; Thu, 12 May 2022 19:06:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652382388; bh=wvLUTuIMgQTvcQXrs4U57mL2ISHtMlc8i3bkcudyddU=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=oHOnjfSblftFf7mckEYu4OwFmrcvKPCGxMPa1xLr4OEbpxYoTKN5NXMvEw/bIAQHh 3pHwiKD4BsP8Fr2aAuNb1D/WTP4YfSlIx7W2QapLVYfwXDm4V1jfOkeMFqVp8cLDbk SC/uE2EVsWrnmFsjFWF0I9bWBoWxe8Uk1f2BzN5Dvmc+1ega5Wvi3w/ItRBcvlX6M6 fch8iQKhO8uib8EqCcAfYkV9Yw56D+cExi+iggPBbG/xDrRaK/n4KbPwwydFA1DJge SvTA+BuGqUlTLO+Tu9iWkg22Y/hNKr4Vl8FNgcTzI7nmRGQkIprnA7sRnvFt0u6J5/ y9hsMkZYbjkfw== Date: Thu, 12 May 2022 14:06:26 -0500 From: Bjorn Helgaas To: Lorenzo Pieralisi Cc: Parshuram Raju Thombare , tjoseph@cadence.com, bhelgaas@google.com, robh@kernel.org, kishon@ti.com, kw@linux.com, mparab@cadence.com, linux-pci@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] PCI: cadence: Clear FLR in device capabilities register Message-ID: <20220512190626.GA862290@bhelgaas> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <165228494389.11307.11313445181760109588.b4-ty@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220512_120630_817080_2FE988E2 X-CRM114-Status: GOOD ( 14.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, May 11, 2022 at 05:02:35PM +0100, Lorenzo Pieralisi wrote: > On Mon, 15 Nov 2021 23:39:16 -0800, Parshuram Raju Thombare wrote: > > From: Parshuram Thombare > > > > Clear FLR (Function Level Reset) from device capabilities > > registers for all physical functions. > > > > During FLR, the Margining Lane Status and Margining Lane Control > > registers should not be reset, as per PCIe specification. > > However, the controller incorrectly resets these registers upon FLR. > > This causes PCISIG compliance FLR test to fail. Hence preventing > > all functions from advertising FLR support if flag quirk_disable_flr > > is set. > > > > [...] > > Applied to pci/cadence, thanks! > > [1/1] PCI: cadence: Clear FLR in device capabilities register > https://git.kernel.org/lpieralisi/pci/c/d3dbd4d862 Obviously you've already seen the kbuild report: https://lore.kernel.org/r/202205120700.X76G7aC2-lkp@intel.com but it looks like most of this patch got lost somehow :) Happy to fix it up for you if you want! Bjorn _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel