Re: [PATCH net-next v2 4/5] net: dt-bindings: Introduce the Qualcomm IPQESS Ethernet controller

Rob Herring
2022-05-18T00:53:50Z

On Sat, May 14, 2022 at 05:06:55PM +0200, Maxime Chevallier wrote:
> Add the DT binding for the IPQESS Ethernet Controller. This is a simple
> controller, only requiring the phy-mode, interrupts, clocks, and
> possibly a MAC address setting.
>
> Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
> ---
> V1->V2:
> - Fixed the example
> - Added reset and clocks
> - Removed generic ethernet attributes
>
> .../devicetree/bindings/net/qcom,ipqess.yaml | 104 ++++++++++++++++++
> 1 file changed, 104 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/qcom,ipqess.yaml
>
> diff --git a/Documentation/devicetree/bindings/net/qcom,ipqess.yaml b/Documentation/devicetree/bindings/net/qcom,ipqess.yaml
> new file mode 100644
> index 000000000000..ea0023509737
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/qcom,ipqess.yaml
> @@ -0,0 +1,104 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/qcom,ipqess.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm IPQ ESS EDMA Ethernet Controller
> +
> +maintainers:
> + - Maxime Chevallier <maxime.chevallier@bootlin.com>
> +
> +allOf:
> + - $ref: "ethernet-controller.yaml#"
> +
> +properties:
> + compatible:
> + const: qcom,ipq4019e-ess-edma
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + minItems: 2
> + maxItems: 32
> + description: One interrupt per tx and rx queue, with up to 16 queues.
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + const: ess

Always kind of pointless to have a single *-names entry when it's just
the block name.

> +
> + resets:
> + maxItems: 1
> +
> + reset-names:
> + const: ess

ditto

> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> + - resets
> + - phy-mode
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + gmac: ethernet@c080000 {
> + compatible = "qcom,ipq4019-ess-edma";
> + reg = <0xc080000 0x8000>;
> + resets = <&gcc ESS_RESET>;
> + reset-names = "ess";
> + clocks = <&gcc GCC_ESS_CLK>;
> + clock-names = "ess";
> + interrupts = <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
> +
> + phy-mode = "internal";
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + pause;
> + asym-pause;
> + };
> + };
> +
> +...
> --
> 2.36.1