From: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
To: <robh+dt@kernel.org>, <joel@jms.id.au>, <andrew@aj.id.au>,
<jk@codeconstruct.com.au>, <a.kartashev@yadro.com>,
<patrick.rudolph@9elements.com>, <dphadke@linux.microsoft.com>,
<linux-aspeed@lists.ozlabs.org>, <openbmc@lists.ozlabs.org>,
<devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Cc: <ryan_chen@aspeedtech.com>
Subject: [PATCH v5 4/4] ARM: dts: aspeed: Add eSPI node
Date: Mon, 16 May 2022 08:54:12 +0800 [thread overview]
Message-ID: <20220516005412.4844-5-chiawei_wang@aspeedtech.com> (raw)
In-Reply-To: <20220516005412.4844-1-chiawei_wang@aspeedtech.com>
Add eSPI to the device tree for Aspeed 5/6th generation SoCs.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
---
arch/arm/boot/dts/aspeed-g5.dtsi | 17 +++++++++++++++++
arch/arm/boot/dts/aspeed-g6.dtsi | 17 +++++++++++++++++
2 files changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 4147b397c883..4b5bb91a0219 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -289,6 +289,23 @@ adc: adc@1e6e9000 {
status = "disabled";
};
+ espi: espi@1e6ee000 {
+ compatible = "aspeed,ast2500-espi", "simple-mfd", "syscon";
+ reg = <0x1e6ee000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e6ee000 0x1000>;
+
+ espi_ctrl: espi-ctrl@0 {
+ compatible = "aspeed,ast2500-espi-ctrl";
+ reg = <0x0 0x800>;
+ interrupts = <23>;
+ clocks = <&syscon ASPEED_CLK_GATE_ESPICLK>;
+ status = "disabled";
+ };
+ };
+
video: video@1e700000 {
compatible = "aspeed,ast2500-video-engine";
reg = <0x1e700000 0x1000>;
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 3d5ce9da42c3..1f14ecad51af 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -384,6 +384,23 @@ adc1: adc@1e6e9100 {
status = "disabled";
};
+ espi: espi@1e6ee000 {
+ compatible = "aspeed,ast2600-espi", "simple-mfd", "syscon";
+ reg = <0x1e6ee000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e6ee000 0x1000>;
+
+ espi_ctrl: espi-ctrl@0 {
+ compatible = "aspeed,ast2600-espi-ctrl";
+ reg = <0x0 0x800>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_ESPICLK>;
+ status = "disabled";
+ };
+ };
+
sbc: secure-boot-controller@1e6f2000 {
compatible = "aspeed,ast2600-sbc";
reg = <0x1e6f2000 0x1000>;
--
2.25.1
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prev parent reply other threads:[~2022-05-16 0:56 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-16 0:54 [PATCH v5 0/4] arm: aspeed: Add eSPI support Chia-Wei Wang
2022-05-16 0:54 ` [PATCH v5 1/4] dt-bindings: aspeed: Add eSPI controller Chia-Wei Wang
2022-05-17 18:31 ` Rob Herring
2022-05-18 0:15 ` ChiaWei Wang
2022-05-18 18:26 ` Rob Herring
2022-05-19 3:10 ` ChiaWei Wang
2022-05-18 6:18 ` Patrick Rudolph
2022-05-16 0:54 ` [PATCH v5 2/4] MAINTAINER: Add ASPEED eSPI driver entry Chia-Wei Wang
2022-05-16 0:54 ` [PATCH v5 3/4] soc: aspeed: Add eSPI driver Chia-Wei Wang
2022-05-18 19:12 ` Christophe JAILLET
2022-05-16 0:54 ` Chia-Wei Wang [this message]
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