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[76.183.134.35]) by smtp.gmail.com with ESMTPSA id z30-20020a056870461e00b000e686d1389fsm5475774oao.57.2022.05.16.08.26.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 May 2022 08:26:54 -0700 (PDT) Date: Mon, 16 May 2022 10:26:51 -0500 From: Chris Morgan To: Peter Geis Cc: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1 6/6] arm64: dts: rockchip: enable sfc controller on Quartz64 Model A Message-ID: <20220516152651.GA18461@wintermute.localdomain> References: <20220511150117.113070-1-pgwipeout@gmail.com> <20220511150117.113070-7-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220511150117.113070-7-pgwipeout@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220516_082701_384418_64DDFCEB X-CRM114-Status: GOOD ( 18.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, May 11, 2022 at 11:01:17AM -0400, Peter Geis wrote: > Add the sfc controller binding for the Quartz64 Model A. This is not > populated by default, so leave it disabled. > > Signed-off-by: Peter Geis > --- > .../boot/dts/rockchip/rk3566-quartz64-a.dts | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > index 71df64655de5..6ec349e7e521 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > @@ -603,6 +603,22 @@ &sdmmc1 { > status = "okay"; > }; > > +&sfc { > + pinctrl-0 = <&fspi_pins>; > + pinctrl-names = "default"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + > + flash@0 { > + compatible = "jedec,spi-nor"; > + reg = <0>; > + spi-max-frequency = <24000000>; > + spi-rx-bus-width = <4>; > + spi-tx-bus-width = <1>; This isn't really a concern, just a comment. Did you test this with the spi-tx-bus-width of 4 by chance? While I did have to use 1 for my implementation (the Odroid Go Advance) the Rockchip engineer I worked with couldn't replicate the issue on his end and we ended up chalking my issues up to an implementation specific problem. I'm only commenting here because I don't want you to think that for this device the tx always has to be 1, of course if your implementation does have issues with a tx of 2 or 4 that's different... Thank you. > + }; > +}; > + > /* spdif is exposed on con40 pin 18 */ > &spdif { > status = "okay"; > -- > 2.25.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel