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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id j9-20020aca3c09000000b00326bab99fe5sm4305839oia.40.2022.05.16.15.49.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 May 2022 15:49:33 -0700 (PDT) Received: (nullmailer pid 3462273 invoked by uid 1000); Mon, 16 May 2022 22:49:32 -0000 Date: Mon, 16 May 2022 17:49:32 -0500 From: Rob Herring To: Hector Martin Cc: "Rafael J. Wysocki" , Viresh Kumar , Sven Peter , Alyssa Rosenzweig , Krzysztof Kozlowski , Stephen Boyd , Ulf Hansson , Marc Zyngier , Mark Kettenis , linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 2/4] dt-bindings: cpufreq: apple,soc-cpufreq: Add binding for Apple SoC cpufreq Message-ID: <20220516224932.GA3452552-robh@kernel.org> References: <20220504075153.185208-1-marcan@marcan.st> <20220504075153.185208-3-marcan@marcan.st> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220504075153.185208-3-marcan@marcan.st> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220516_154935_214855_80787C0E X-CRM114-Status: GOOD ( 22.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, May 04, 2022 at 04:51:51PM +0900, Hector Martin wrote: > This binding represents the cpufreq/DVFS hardware present in Apple SoCs. > The hardware has an independent controller per CPU cluster, but we > represent them as a single cpufreq node since there can only be one > systemwide cpufreq device (and since in the future, interactions with > memory controller performance states will also involve cooperation > between multiple frequency domains). > > Signed-off-by: Hector Martin > --- > .../bindings/cpufreq/apple,soc-cpufreq.yaml | 121 ++++++++++++++++++ > 1 file changed, 121 insertions(+) > create mode 100644 Documentation/devicetree/bindings/cpufreq/apple,soc-cpufreq.yaml > > diff --git a/Documentation/devicetree/bindings/cpufreq/apple,soc-cpufreq.yaml b/Documentation/devicetree/bindings/cpufreq/apple,soc-cpufreq.yaml > new file mode 100644 > index 000000000000..f398c1bd5de5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/cpufreq/apple,soc-cpufreq.yaml > @@ -0,0 +1,121 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/cpufreq/apple,soc-cpufreq.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Apple SoC cpufreq device > + > +maintainers: > + - Hector Martin > + > +description: | > + Apple SoCs (e.g. M1) have a per-cpu-cluster DVFS controller that is part of > + the cluster management register block. This binding uses the standard > + operating-points-v2 table to define the CPU performance states, with the > + opp-level property specifying the hardware p-state index for that level. > + > +properties: > + compatible: > + items: > + - enum: > + - apple,t8103-soc-cpufreq > + - apple,t6000-soc-cpufreq > + - const: apple,soc-cpufreq > + > + reg: > + minItems: 1 > + maxItems: 6 > + description: One register region per CPU cluster DVFS controller > + > + reg-names: > + minItems: 1 > + items: > + - const: cluster0 > + - const: cluster1 > + - const: cluster2 > + - const: cluster3 > + - const: cluster4 > + - const: cluster5 > + > + '#freq-domain-cells': > + const: 1 Copied QCom it seems. Use 'performance-domains' which is the common binding. > + > +required: > + - compatible > + - reg > + - reg-names > + - '#freq-domain-cells' > + > +additionalProperties: false > + > +examples: > + - | > + // This example shows a single CPU per domain and 2 domains, > + // with two p-states per domain. > + // Shipping hardware has 2-4 CPUs per domain and 2-6 domains. > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu@0 { > + compatible = "apple,icestorm"; > + device_type = "cpu"; > + reg = <0x0 0x0>; > + operating-points-v2 = <&ecluster_opp>; > + apple,freq-domain = <&cpufreq_hw 0>; > + }; > + > + cpu@10100 { > + compatible = "apple,firestorm"; > + device_type = "cpu"; > + reg = <0x0 0x10100>; > + operating-points-v2 = <&pcluster_opp>; > + apple,freq-domain = <&cpufreq_hw 1>; > + }; > + }; > + > + ecluster_opp: opp-table-0 { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp01 { > + opp-hz = /bits/ 64 <600000000>; > + opp-level = <1>; > + clock-latency-ns = <7500>; > + }; > + opp02 { > + opp-hz = /bits/ 64 <972000000>; > + opp-level = <2>; > + clock-latency-ns = <22000>; > + }; > + }; > + > + pcluster_opp: opp-table-1 { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp01 { > + opp-hz = /bits/ 64 <600000000>; > + opp-level = <1>; > + clock-latency-ns = <8000>; > + }; > + opp02 { > + opp-hz = /bits/ 64 <828000000>; > + opp-level = <2>; > + clock-latency-ns = <19000>; > + }; > + }; > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpufreq_hw: cpufreq@210e20000 { > + compatible = "apple,t8103-soc-cpufreq", "apple,soc-cpufreq"; > + reg = <0x2 0x10e20000 0 0x1000>, > + <0x2 0x11e20000 0 0x1000>; > + reg-names = "cluster0", "cluster1"; > + #freq-domain-cells = <1>; > + }; > + }; > -- > 2.35.1 > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel