From: Fabien Parent <fparent@baylibre.com>
To: Sean Wang <sean.wang@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>,
Matthias Brugger <matthias.bgg@gmail.com>
Cc: Fabien Parent <fparent@baylibre.com>,
linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 2/2] pinctrl: mediatek: mt8365: use MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk
Date: Mon, 30 May 2022 14:34:25 +0200 [thread overview]
Message-ID: <20220530123425.689459-2-fparent@baylibre.com> (raw)
In-Reply-To: <20220530123425.689459-1-fparent@baylibre.com>
On MT8365, the GPIO64 modes cannot be set using the SET/CLR register.
Use the MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk to workaround it.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
drivers/pinctrl/mediatek/pinctrl-mt8365.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c
index 57f37a294063..a49fa685f5f5 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c
@@ -454,6 +454,7 @@ static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = {
.ap_num = 160,
.db_cnt = 160,
},
+ .quirks = MTK_PINCTRL_MODE_SET_CLR_BROKEN,
};
static const struct of_device_id mt8365_pctrl_match[] = {
--
2.36.1
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next prev parent reply other threads:[~2022-05-30 12:36 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-30 12:34 [PATCH 1/2] pinctrl: mediatek: common: add quirk for broken set/clr modes Fabien Parent
2022-05-30 12:34 ` Fabien Parent [this message]
2022-06-10 11:19 ` AngeloGioacchino Del Regno
2022-06-15 13:23 ` Linus Walleij
2022-07-01 7:35 ` Markus Schneider-Pargmann
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