From: "Clément Léger" <clement.leger@bootlin.com>
To: Russell King <linux@armlinux.org.uk>,
Nicolas Ferre <nicolas.ferre@microchip.com>,
Alexandre Belloni <alexandre.belloni@bootlin.com>,
Claudiu Beznea <claudiu.beznea@microchip.com>
Cc: "Clément Léger" <clement.leger@bootlin.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>
Subject: [PATCH 2/2] ARM: at91: setup outer cache .write_sec() callback if needed
Date: Mon, 6 Jun 2022 16:57:01 +0200 [thread overview]
Message-ID: <20220606145701.185552-3-clement.leger@bootlin.com> (raw)
In-Reply-To: <20220606145701.185552-1-clement.leger@bootlin.com>
When running under OP-TEE, the L2 cache is configured by OP-TEE and the
sam platform code does not allow any modification yet. Setup a dummy
.write_sec() callback to avoid triggering exceptions when Linux tries
to modify the L2 cache configuration.
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
---
arch/arm/mach-at91/sama5.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/mach-at91/sama5.c b/arch/arm/mach-at91/sama5.c
index de5dd28b392e..d1a9e940a785 100644
--- a/arch/arm/mach-at91/sama5.c
+++ b/arch/arm/mach-at91/sama5.c
@@ -9,13 +9,27 @@
#include <linux/of.h>
#include <linux/of_platform.h>
+#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
+#include <asm/outercache.h>
#include <asm/system_misc.h>
#include "generic.h"
#include "sam_secure.h"
+static void sama5_l2c310_write_sec(unsigned long val, unsigned reg)
+{
+ /* OP-TEE configures the L2 cache and does not allow modifying it yet */
+}
+
+static void __init sama5_secure_cache_init(void)
+{
+ sam_secure_init();
+ if (sam_linux_is_in_normal_world())
+ outer_cache.write_sec = sama5_l2c310_write_sec;
+}
+
static void __init sama5_dt_device_init(void)
{
of_platform_default_populate(NULL, NULL, NULL);
@@ -30,6 +44,7 @@ static const char *const sama5_dt_board_compat[] __initconst = {
DT_MACHINE_START(sama5_dt, "Atmel SAMA5")
/* Maintainer: Atmel */
.init_machine = sama5_dt_device_init,
+ .init_early = sama5_secure_cache_init,
.dt_compat = sama5_dt_board_compat,
MACHINE_END
@@ -41,6 +56,7 @@ static const char *const sama5_alt_dt_board_compat[] __initconst = {
DT_MACHINE_START(sama5_alt_dt, "Atmel SAMA5")
/* Maintainer: Atmel */
.init_machine = sama5_dt_device_init,
+ .init_early = sama5_secure_cache_init,
.dt_compat = sama5_alt_dt_board_compat,
.l2c_aux_mask = ~0UL,
MACHINE_END
@@ -60,6 +76,7 @@ static const char *const sama5d2_compat[] __initconst = {
DT_MACHINE_START(sama5d2, "Atmel SAMA5")
/* Maintainer: Atmel */
.init_machine = sama5d2_init,
+ .init_early = sama5_secure_cache_init,
.dt_compat = sama5d2_compat,
.l2c_aux_mask = ~0UL,
MACHINE_END
--
2.36.1
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next prev parent reply other threads:[~2022-06-06 14:59 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-06 14:56 [PATCH 0/2] ARM: at91: add support for L2 cache write_sec() callback Clément Léger
2022-06-06 14:57 ` [PATCH 1/2] ARM: at91: add sam_linux_is_in_normal_world() function Clément Léger
2022-07-04 6:19 ` Claudiu.Beznea
2022-07-04 17:34 ` clement.leger
2022-07-20 8:29 ` Claudiu.Beznea
2022-06-06 14:57 ` Clément Léger [this message]
2022-07-04 6:39 ` [PATCH 2/2] ARM: at91: setup outer cache .write_sec() callback if needed Claudiu.Beznea
2022-07-20 8:30 ` Claudiu.Beznea
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