From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 17B66C43334 for ; Sat, 11 Jun 2022 17:38:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=FfwOwug0RafGML3KNhIhuisw7wbzKPW34Fs7+x/Teik=; b=W82HQ9KdLjNiCi S6CC8XO3sBKS5lydZML2U951n/PctPTut+7nKdtFz27WRO5SEOeFWA+pyEegKcYvnYMW49ZRo8rNj EgPLUF8i2lp0qLgRLiXXs2qG5scaI2MjtBqKp1LfHj75/wBV3mOjHfndrNqvhalzyYpqbtvonGQLO HuNQQTiInYNNETQKT8jwjSVwiHTwX1MOqXy5rLoxzBU6Gtp2RFYxDzhS20Ex9MS+iSmNlqUOG57fD iMX1sd4xBxSiB4nnN+RG7FkONafQMbntT75NGT/6bVXwtxznspRqsBh0ralljCiJCc3FAHPWLanR+ oIY16zJQQM6Apnz1OmjQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o052u-00DzOd-8W; Sat, 11 Jun 2022 17:37:12 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o052r-00DzOB-JA for linux-arm-kernel@lists.infradead.org; Sat, 11 Jun 2022 17:37:11 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E2DF961027; Sat, 11 Jun 2022 17:37:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 98A10C34116; Sat, 11 Jun 2022 17:37:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1654969028; bh=87s5IER2Hkii2UwGwmS+MjR5p1EgqGo8RMcZqPW65e4=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=XriqISjLhSiM1lS74ptrk8SHbnrzVrKf0BalmgOhxlZXfO1dUwyXqS7SWE9Wkl8ji 3ZIukpf9swW+uROIXAdpH/NvYkYTh10KbyQuThF9Xa95I44B/a4BYPbcr0fOnSmqNx KsYGZgPcyh5jw+N7Oc/gTBQi98msaUJgJ1mHHJQ+U6+H+7ydk2TfxlJILvLWHD52qN qFQpSlZFZc7bQOj5zMOQgqZFnG2SqCDRxgkVT8m9R7ts3uj3MgKWdPhNVumAQYjbsh cf5UjtJP5qG4zbYtq4Upn5K4c8KcMnHJ1z/SMOxtCgzsk3ha3LS0fIlQ4sQwPZ+IZ8 PNYH1dtMxsVMA== Date: Sat, 11 Jun 2022 18:46:17 +0100 From: Jonathan Cameron To: Claudiu Beznea Subject: Re: [PATCH 04/16] iio: adc: at91-sama5d2_adc: handle different EMR.OSR for different hw versions Message-ID: <20220611184617.0aa9eb85@jic23-huawei> In-Reply-To: <20220609083213.1795019-5-claudiu.beznea@microchip.com> References: <20220609083213.1795019-1-claudiu.beznea@microchip.com> <20220609083213.1795019-5-claudiu.beznea@microchip.com> X-Mailer: Claws Mail 4.1.0 (GTK 3.24.34; x86_64-pc-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220611_103709_762383_F75A104A X-CRM114-Status: GOOD ( 27.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, alexandre.belloni@bootlin.com, lars@metafoo.de, ludovic.desroches@atmel.com, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, eugen.hristev@microchip.com, krzk+dt@kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 9 Jun 2022 11:32:01 +0300 Claudiu Beznea wrote: > SAMA7G5 introduces 64 and 256 oversampling rates. Due to this EMR.OSR is 3 > bits long. Change the code to reflect this. Commit prepares the code > for the addition of 64 and 256 oversampling rates. > > Signed-off-by: Claudiu Beznea > --- > drivers/iio/adc/at91-sama5d2_adc.c | 55 ++++++++++++++++++++++-------- > 1 file changed, 40 insertions(+), 15 deletions(-) > > diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c > index b76328da0cb2..1ceab097335c 100644 > --- a/drivers/iio/adc/at91-sama5d2_adc.c > +++ b/drivers/iio/adc/at91-sama5d2_adc.c > @@ -138,8 +138,7 @@ struct at91_adc_reg_layout { > /* Extended Mode Register */ > u16 EMR; > /* Extended Mode Register - Oversampling rate */ > -#define AT91_SAMA5D2_EMR_OSR(V) ((V) << 16) > -#define AT91_SAMA5D2_EMR_OSR_MASK GENMASK(17, 16) > +#define AT91_SAMA5D2_EMR_OSR(V, M) (((V) << 16) & (M)) > #define AT91_SAMA5D2_EMR_OSR_1SAMPLES 0 > #define AT91_SAMA5D2_EMR_OSR_4SAMPLES 1 > #define AT91_SAMA5D2_EMR_OSR_16SAMPLES 2 > @@ -403,6 +402,8 @@ static const struct at91_adc_reg_layout sama7g5_layout = { > * @max_index: highest channel index (highest index may be higher > * than the total channel number) > * @hw_trig_cnt: number of possible hardware triggers > + * @osr_mask: oversampling ratio bitmask on EMR register > + * @osr_vals: available oversampling rates > */ > struct at91_adc_platform { > const struct at91_adc_reg_layout *layout; > @@ -414,6 +415,8 @@ struct at91_adc_platform { > unsigned int max_channels; > unsigned int max_index; > unsigned int hw_trig_cnt; > + unsigned int osr_mask; > + unsigned int osr_vals; > }; > > /** > @@ -612,6 +615,10 @@ static const struct at91_adc_platform sama5d2_platform = { > .max_index = AT91_SAMA5D2_MAX_CHAN_IDX, > #define AT91_SAMA5D2_HW_TRIG_CNT 3 > .hw_trig_cnt = AT91_SAMA5D2_HW_TRIG_CNT, > + .osr_mask = GENMASK(17, 16), > + .osr_vals = BIT(AT91_SAMA5D2_EMR_OSR_1SAMPLES) | > + BIT(AT91_SAMA5D2_EMR_OSR_4SAMPLES) | > + BIT(AT91_SAMA5D2_EMR_OSR_16SAMPLES), > }; > > static const struct at91_adc_platform sama7g5_platform = { > @@ -627,6 +634,10 @@ static const struct at91_adc_platform sama7g5_platform = { > .max_index = AT91_SAMA7G5_MAX_CHAN_IDX, > #define AT91_SAMA7G5_HW_TRIG_CNT 3 > .hw_trig_cnt = AT91_SAMA7G5_HW_TRIG_CNT, > + .osr_mask = GENMASK(18, 16), > + .osr_vals = BIT(AT91_SAMA5D2_EMR_OSR_1SAMPLES) | > + BIT(AT91_SAMA5D2_EMR_OSR_4SAMPLES) | > + BIT(AT91_SAMA5D2_EMR_OSR_16SAMPLES), > }; > > static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan) > @@ -725,34 +736,45 @@ static void at91_adc_eoc_ena(struct at91_adc_state *st, unsigned int channel) > at91_adc_writel(st, EOC_IER, BIT(channel)); > } > > -static void at91_adc_config_emr(struct at91_adc_state *st) > +static int at91_adc_config_emr(struct at91_adc_state *st, > + u32 oversampling_ratio) > { > /* configure the extended mode register */ > unsigned int emr = at91_adc_readl(st, EMR); > + unsigned int osr_mask = st->soc_info.platform->osr_mask; > + unsigned int osr_vals = st->soc_info.platform->osr_vals; > > /* select oversampling per single trigger event */ > emr |= AT91_SAMA5D2_EMR_ASTE(1); > > /* delete leftover content if it's the case */ > - emr &= ~AT91_SAMA5D2_EMR_OSR_MASK; > + emr &= ~osr_mask; > > /* select oversampling ratio from configuration */ > - switch (st->oversampling_ratio) { > + switch (oversampling_ratio) { > case AT91_OSR_1SAMPLES: > - emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_1SAMPLES) & > - AT91_SAMA5D2_EMR_OSR_MASK; > + if (!(osr_vals & BIT(AT91_SAMA5D2_EMR_OSR_1SAMPLES))) > + return -EINVAL; > + emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_1SAMPLES, > + osr_mask); > break; > case AT91_OSR_4SAMPLES: > - emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_4SAMPLES) & > - AT91_SAMA5D2_EMR_OSR_MASK; > + if (!(osr_vals & BIT(AT91_SAMA5D2_EMR_OSR_4SAMPLES))) > + return -EINVAL; > + emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_4SAMPLES, > + osr_mask); > break; > case AT91_OSR_16SAMPLES: > - emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES) & > - AT91_SAMA5D2_EMR_OSR_MASK; > + if (!(osr_vals & BIT(AT91_SAMA5D2_EMR_OSR_16SAMPLES))) > + return -EINVAL; > + emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES, > + osr_mask); > break; > } > > at91_adc_writel(st, EMR, emr); > + > + return 0; > } > > static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val) > @@ -1643,6 +1665,7 @@ static int at91_adc_write_raw(struct iio_dev *indio_dev, > int val, int val2, long mask) > { > struct at91_adc_state *st = iio_priv(indio_dev); > + int ret = 0; > > if (iio_buffer_enabled(indio_dev)) > return -EBUSY; > @@ -1656,12 +1679,14 @@ static int at91_adc_write_raw(struct iio_dev *indio_dev, > mutex_lock(&st->lock); > if (val == st->oversampling_ratio) > goto unlock; > - st->oversampling_ratio = val; > /* update ratio */ > - at91_adc_config_emr(st); > + ret = at91_adc_config_emr(st, val); > + if (ret) > + goto unlock; > + st->oversampling_ratio = val; Good. I looked at the old ordering when reviewing earlier patch and thought that doesn't look good :) However, now you hae the value passed to at91_adc_config_emr() perhaps you can drop the checking that it is a possible value from above this call and move it to the default case on the switch statement in there? (noticed on later patch, where that context is visible). > unlock: > mutex_unlock(&st->lock); > - return 0; > + return ret; > case IIO_CHAN_INFO_SAMP_FREQ: > if (val < st->soc_info.min_sample_rate || > val > st->soc_info.max_sample_rate) > @@ -1834,7 +1859,7 @@ static void at91_adc_hw_init(struct iio_dev *indio_dev) > at91_adc_setup_samp_freq(indio_dev, st->soc_info.min_sample_rate); > > /* configure extended mode register */ > - at91_adc_config_emr(st); > + at91_adc_config_emr(st, st->oversampling_ratio); > } > > static ssize_t at91_adc_get_fifo_state(struct device *dev, _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel