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Tue, 14 Jun 2022 03:48:51 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 14 Jun 2022 03:48:50 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 14 Jun 2022 03:48:50 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 25E8mnC0016187; Tue, 14 Jun 2022 03:48:50 -0500 Date: Tue, 14 Jun 2022 14:18:49 +0530 From: Pratyush Yadav To: Brad Larson CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v5 11/15] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC Message-ID: <20220614084849.oodxh6cthysga5iq@ti.com> References: <20220613195658.5607-1-brad@pensando.io> <20220613195658.5607-12-brad@pensando.io> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220613195658.5607-12-brad@pensando.io> X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220614_014919_787282_25925D48 X-CRM114-Status: GOOD ( 26.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Brad, On 13/06/22 12:56PM, Brad Larson wrote: > From: Brad Larson > > The AMD Pensando Elba SoC has the Cadence QSPI controller integrated. > > The quirk CQSPI_NEEDS_APB_AHB_HAZARD_WAR is added and if enabled > a dummy readback from the controller is performed to ensure > synchronization. > > Signed-off-by: Brad Larson > --- > drivers/spi/spi-cadence-quadspi.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c > index 72b1a5a2298c..ebb77ea8e6ba 100644 > --- a/drivers/spi/spi-cadence-quadspi.c > +++ b/drivers/spi/spi-cadence-quadspi.c > @@ -39,6 +39,7 @@ > #define CQSPI_DISABLE_DAC_MODE BIT(1) > #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) > #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) > +#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(4) > > /* Capabilities */ > #define CQSPI_SUPPORTS_OCTAL BIT(0) > @@ -87,6 +88,7 @@ struct cqspi_st { > bool use_dma_read; > u32 pd_dev_id; > bool wr_completion; > + bool apb_ahb_hazard; > }; > > struct cqspi_driver_platdata { > @@ -952,6 +954,13 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, > if (cqspi->wr_delay) > ndelay(cqspi->wr_delay); > > + /* > + * If a hazard exists between the APB and AHB interfaces, perform a > + * dummy readback from the controller to ensure synchronization. > + */ This is needed for TI's SoCs as well. APB and AHB accesses are independent of each other on the interconnect and can be racy. I wrote a couple patches [0][1] to fix this on TI's fork. I never got around to sending them upstream. It would be great if you can pick those up. They fix the race in all paths, not just indirect write. I would also prefer if we do this unconditionally. I don't think it has much downside even on platforms that do not strictly need this. [0] https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/commit/drivers/spi/spi-cadence-quadspi.c?h=ti-linux-5.10.y&id=027f03a8512086e5ef05dc4e4ff53b2628848f95 [1] https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/commit/drivers/spi/spi-cadence-quadspi.c?h=ti-linux-5.10.y&id=4c367e58bab7d3f9c470c3778441f73546f20398 > + if (cqspi->apb_ahb_hazard) > + (void)readl(reg_base + CQSPI_REG_INDIRECTWR); > + > while (remaining > 0) { > size_t write_words, mod_bytes; > > @@ -1667,6 +1676,8 @@ static int cqspi_probe(struct platform_device *pdev) > cqspi->use_dma_read = true; > if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION) > cqspi->wr_completion = false; > + if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) > + cqspi->apb_ahb_hazard = true; > > if (of_device_is_compatible(pdev->dev.of_node, > "xlnx,versal-ospi-1.0")) > @@ -1789,6 +1800,10 @@ static const struct cqspi_driver_platdata versal_ospi = { > .get_dma_status = cqspi_get_versal_dma_status, > }; > > +static const struct cqspi_driver_platdata pen_cdns_qspi = { > + .quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE, > +}; > + > static const struct of_device_id cqspi_dt_ids[] = { > { > .compatible = "cdns,qspi-nor", > @@ -1814,6 +1829,10 @@ static const struct of_device_id cqspi_dt_ids[] = { > .compatible = "intel,socfpga-qspi", > .data = &socfpga_qspi, > }, > + { > + .compatible = "amd,pensando-elba-qspi", > + .data = &pen_cdns_qspi, > + }, > { /* end of table */ } > }; > > -- > 2.17.1 > -- Regards, Pratyush Yadav Texas Instruments Inc. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel