From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 06477C43334 for ; Thu, 16 Jun 2022 23:15:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Reply-To:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qAfB80KhKN2J/+RWAxqjATAXvC9sW+7PGHqt8H+wdRA=; b=o75U0FKfqnlC2b ix9ySeOp7El+pYjDCKy1pJ7bNvRbpYeLmce+gkbl8VwUSDWdiPZX9eRRMPkKlVKFvic/swHyJgGDF CNdVlV5PiztYNhauKr2tjSSImq96SHG42ddTPZwoZwTitln8PgT5c1yWi5RdoibMgHprHr54Ln4kG mNEZiOQx5NVLIjg5iduPtGDf9Ywi9OytGGFD2PLFK/H8cHo992OryN8W8G8Cuv8YjeVKY8W2wrBkt TTDWSTJ6bimhBJ5cWFTgJdt266Ng31xeMUCOhHg4G35Oqx+ikKYSyaBKMABuQQoUgQLsG3YsenPqd 3VIoBi9OmCyUTiV65d8w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o1yga-004jhE-KR; Thu, 16 Jun 2022 23:14:00 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o1ygX-004jfm-2Z for linux-arm-kernel@lists.infradead.org; Thu, 16 Jun 2022 23:13:58 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 78E15B82618; Thu, 16 Jun 2022 23:13:52 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 38C38C34114; Thu, 16 Jun 2022 23:13:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655421231; bh=Ejx2DTxm/7UIK+VC+L1RteDR9DsxwnAj5eYVDoMkO4Y=; h=Date:From:To:Cc:Subject:Reply-To:References:In-Reply-To:From; b=eaA7OMkSsxkf1sWe94biqKhLOdZAJNvCqlCufdt04pueooz+KhapEvI2RSVqaKGuL AIiDRWSqe/kkFL4d6TRx/xAyYAnbP9gZhqSO5WY169uHl4aRjU3TKHb94QlcQxNitj orb+TbBIoSSnTPsFRbvNT4thWIdFL/qeOAyKXJnBE2e3+o/Kb+FU8xYc2pB6BJ2ssg jwlRA4yCaomvIjmQRRjXWrG1fjLsvljLLdfrrihO93mGrzBBZyBOl+nG8MQto28D/Z UYBvFv0auHw6hxwTSf/RJKzuqWatwgeco/wVAA3EwGfQvmaDkqIx6IuTKtMASDBvIA ibPJM7CD3G26Q== Received: by paulmck-ThinkPad-P17-Gen-1.home (Postfix, from userid 1000) id C6D8F5C1363; Thu, 16 Jun 2022 16:13:50 -0700 (PDT) Date: Thu, 16 Jun 2022 16:13:50 -0700 From: "Paul E. McKenney" To: Marco Elver Cc: Kefeng Wang , catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, Jonathan Corbet , linux-doc@vger.kernel.org, arnd@arndb.de, Peter Zijlstra Subject: Re: [PATCH v4 1/2] asm-generic: Add memory barrier dma_mb() Message-ID: <20220616231350.GA1790663@paulmck-ThinkPad-P17-Gen-1> References: <20220523113126.171714-1-wangkefeng.wang@huawei.com> <20220523113126.171714-2-wangkefeng.wang@huawei.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220616_161357_429497_328A87CA X-CRM114-Status: GOOD ( 34.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: paulmck@kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, May 23, 2022 at 01:35:27PM +0200, Marco Elver wrote: > On Mon, 23 May 2022 at 13:21, Kefeng Wang wrote: > > > > The memory barrier dma_mb() is introduced by commit a76a37777f2c > > ("iommu/arm-smmu-v3: Ensure queue is read after updating prod pointer"), > > which is used to ensure that prior (both reads and writes) accesses > > to memory by a CPU are ordered w.r.t. a subsequent MMIO write. > > > > Reviewed-by: Arnd Bergmann # for asm-generic > > Signed-off-by: Kefeng Wang > > Reviewed-by: Marco Elver Just checking... Did these ever get picked up? It was suggested that they go up via the arm64 tree, if I remember correctly. Thanx, Paul > > --- > > Documentation/memory-barriers.txt | 11 ++++++----- > > include/asm-generic/barrier.h | 8 ++++++++ > > 2 files changed, 14 insertions(+), 5 deletions(-) > > > > diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt > > index b12df9137e1c..832b5d36e279 100644 > > --- a/Documentation/memory-barriers.txt > > +++ b/Documentation/memory-barriers.txt > > @@ -1894,6 +1894,7 @@ There are some more advanced barrier functions: > > > > (*) dma_wmb(); > > (*) dma_rmb(); > > + (*) dma_mb(); > > > > These are for use with consistent memory to guarantee the ordering > > of writes or reads of shared memory accessible to both the CPU and a > > @@ -1925,11 +1926,11 @@ There are some more advanced barrier functions: > > The dma_rmb() allows us guarantee the device has released ownership > > before we read the data from the descriptor, and the dma_wmb() allows > > us to guarantee the data is written to the descriptor before the device > > - can see it now has ownership. Note that, when using writel(), a prior > > - wmb() is not needed to guarantee that the cache coherent memory writes > > - have completed before writing to the MMIO region. The cheaper > > - writel_relaxed() does not provide this guarantee and must not be used > > - here. > > + can see it now has ownership. The dma_mb() implies both a dma_rmb() and > > + a dma_wmb(). Note that, when using writel(), a prior wmb() is not needed > > + to guarantee that the cache coherent memory writes have completed before > > + writing to the MMIO region. The cheaper writel_relaxed() does not provide > > + this guarantee and must not be used here. > > > > See the subsection "Kernel I/O barrier effects" for more information on > > relaxed I/O accessors and the Documentation/core-api/dma-api.rst file for > > diff --git a/include/asm-generic/barrier.h b/include/asm-generic/barrier.h > > index fd7e8fbaeef1..961f4d88f9ef 100644 > > --- a/include/asm-generic/barrier.h > > +++ b/include/asm-generic/barrier.h > > @@ -38,6 +38,10 @@ > > #define wmb() do { kcsan_wmb(); __wmb(); } while (0) > > #endif > > > > +#ifdef __dma_mb > > +#define dma_mb() do { kcsan_mb(); __dma_mb(); } while (0) > > +#endif > > + > > #ifdef __dma_rmb > > #define dma_rmb() do { kcsan_rmb(); __dma_rmb(); } while (0) > > #endif > > @@ -65,6 +69,10 @@ > > #define wmb() mb() > > #endif > > > > +#ifndef dma_mb > > +#define dma_mb() mb() > > +#endif > > + > > #ifndef dma_rmb > > #define dma_rmb() rmb() > > #endif > > -- > > 2.35.3 > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel