From: Nancy.Lin <nancy.lin@mediatek.com>
To: Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
<wim@linux-watchdog.org>,
"AngeloGioacchino Del Regno"
<angelogioacchino.delregno@collabora.com>, <linux@roeck-us.net>
Cc: David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
"Nathan Chancellor" <nathan@kernel.org>,
Nick Desaulniers <ndesaulniers@google.com>,
"Nancy . Lin" <nancy.lin@mediatek.com>,
"jason-jh . lin" <jason-jh.lin@mediatek.com>,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<dri-devel@lists.freedesktop.org>, <llvm@lists.linux.dev>,
<singo.chang@mediatek.com>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>
Subject: [PATCH v23 08/10] soc: mediatek: mmsys: add reset control for MT8195 vdosys1
Date: Mon, 20 Jun 2022 17:17:59 +0800 [thread overview]
Message-ID: <20220620091801.27680-9-nancy.lin@mediatek.com> (raw)
In-Reply-To: <20220620091801.27680-1-nancy.lin@mediatek.com>
MT8195 vdosys1 has more than 32 reset bits and a different reset base
than other chips. Add the number of reset bits and reset base in mmsys
private data.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 1 +
drivers/soc/mediatek/mtk-mmsys.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 454944a9409c..a6652ae63431 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -75,6 +75,7 @@
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
+#define MT8195_VDO1_SW0_RST_B 0x1d0
#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
#define MT8195_VDO1_HDR_TOP_CFG 0xd00
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index ec4f2d90c05a..9bbf0103b225 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -154,6 +154,8 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.clk_driver = "clk-mt8195-vdo1",
.routes = mmsys_mt8195_vdo1_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8195_vdo1_routing_table),
+ .sw0_rst_offset = MT8195_VDO1_SW0_RST_B,
+ .num_resets = 64,
};
static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
--
2.18.0
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next prev parent reply other threads:[~2022-06-20 9:23 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-20 9:17 [PATCH v23 00/10] Add MediaTek SoC(vdosys1) support for mt8195 Nancy.Lin
2022-06-20 9:17 ` [PATCH v23 01/10] dt-bindings: reset: mt8195: add vdosys1 reset control bit Nancy.Lin
2022-06-20 9:17 ` [PATCH v23 02/10] soc: mediatek: add mtk-mmsys ethdr and mdp_rdma components Nancy.Lin
2022-06-20 9:17 ` [PATCH v23 03/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 Nancy.Lin
2022-06-20 9:17 ` [PATCH v23 04/10] soc: mediatek: add mtk_mmsys_update_bits API Nancy.Lin
2022-06-22 3:01 ` CK Hu
2022-06-22 9:10 ` Nancy.Lin
2022-06-20 9:17 ` [PATCH v23 05/10] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1 Nancy.Lin
2022-06-20 9:17 ` [PATCH v23 06/10] soc: mediatek: add cmdq support of " Nancy.Lin
2022-06-22 3:09 ` CK Hu
2022-06-20 9:17 ` [PATCH v23 07/10] soc: mediatek: mmsys: add mmsys for support 64 reset bits Nancy.Lin
2022-06-20 9:17 ` Nancy.Lin [this message]
2022-06-20 9:18 ` [PATCH v23 09/10] soc: mediatek: add mtk-mutex component - dp_intf1 Nancy.Lin
2022-06-20 9:18 ` [PATCH v23 10/10] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Nancy.Lin
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