From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
Joey Gouly <joey.gouly@arm.com>,
linux-arm-kernel@lists.infradead.org,
Mark Brown <broonie@kernel.org>
Subject: [PATCH v4 19/26] arm64/sysreg: Convert ID_AA64ISAR2_EL1 to automatic generation
Date: Mon, 20 Jun 2022 13:44:00 +0100 [thread overview]
Message-ID: <20220620124407.482398-20-broonie@kernel.org> (raw)
In-Reply-To: <20220620124407.482398-1-broonie@kernel.org>
Automatically generate defines for ID_AA64ISAR2_EL1, using the definitions
in DDI0487H.a. No functional changes.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 27 ---------------------------
arch/arm64/tools/sysreg | 33 +++++++++++++++++++++++++++++++++
2 files changed, 33 insertions(+), 27 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 089e2da3a5a9..a8d882b8e2a2 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -201,8 +201,6 @@
#define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4)
#define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5)
-#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2)
-
#define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
#define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
#define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
@@ -699,31 +697,6 @@
/* Position the attr at the correct index */
#define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8))
-/* id_aa64isar2 */
-#define ID_AA64ISAR2_EL1_BC_SHIFT 28
-#define ID_AA64ISAR2_EL1_APA3_SHIFT 12
-#define ID_AA64ISAR2_EL1_GPA3_SHIFT 8
-#define ID_AA64ISAR2_EL1_RPRES_SHIFT 4
-#define ID_AA64ISAR2_EL1_WFxT_SHIFT 0
-
-/*
- * Value 0x1 has been removed from the architecture, and is
- * reserved, but has not yet been removed from the ARM ARM
- * as of ARM DDI 0487G.b.
- */
-#define ID_AA64ISAR2_EL1_WFxT_NI 0x0
-#define ID_AA64ISAR2_EL1_WFxT_IMP 0x2
-
-#define ID_AA64ISAR2_EL1_APA3_NI 0x0
-#define ID_AA64ISAR2_EL1_APA3_PAuth 0x1
-#define ID_AA64ISAR2_EL1_APA3_EPAC 0x2
-#define ID_AA64ISAR2_EL1_APA3_PAuth2 0x3
-#define ID_AA64ISAR2_EL1_APA3_FPAC 0x4
-#define ID_AA64ISAR2_EL1_APA3_FPACCOMBINE 0x5
-
-#define ID_AA64ISAR2_EL1_GPA3_NI 0x0
-#define ID_AA64ISAR2_EL1_GPA3_IMP 0x1
-
/* id_aa64pfr0 */
#define ID_AA64PFR0_CSV3_SHIFT 60
#define ID_AA64PFR0_CSV2_SHIFT 56
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 29d081b3dcd2..93ea9dff4d4b 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -193,8 +193,41 @@ Enum 3:0 DPB
0b0010 DPB2
EndEnum
EndSysreg
+
+Sysreg ID_AA64ISAR2_EL1 3 0 0 6 2
+Res0 63:28
+Enum 27:24 PAC_frac
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 23:20 BC
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 19:16 MOPS
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 15:12 APA3
+ 0b0000 NI
+ 0b0001 PAuth
+ 0b0010 EPAC
+ 0b0011 PAuth2
+ 0b0100 FPAC
+ 0b0101 FPACCOMBINE
+EndEnum
+Enum 11:8 GPA3
+ 0b0000 NI
0b0001 IMP
EndEnum
+Enum 7:4 RPRES
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 3:0 WFxT
+ 0b0000 NI
+ 0b0010 IMP
+EndEnum
EndSysreg
Sysreg SCTLR_EL1 3 0 1 0 0
--
2.30.2
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next prev parent reply other threads:[~2022-06-20 13:02 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-20 12:43 [PATCH v4 00/26] arm64/sysreg: More system register generation Mark Brown
2022-06-20 12:43 ` [PATCH v4 01/26] arm64/cpuinfo: Restore define for AIVIVT cache type Mark Brown
2022-06-22 11:09 ` Mark Rutland
2022-06-22 12:04 ` Mark Brown
2022-06-23 14:08 ` Mark Rutland
2022-06-23 14:30 ` Mark Brown
2022-06-23 14:36 ` Mark Rutland
2022-06-20 12:43 ` [PATCH v4 02/26] arm64/sysreg: Add LINKER_SCRIPT guards for sysreg.h Mark Brown
2022-06-22 11:11 ` Mark Rutland
2022-06-22 11:19 ` Mark Brown
2022-06-22 15:20 ` Mark Rutland
2022-06-20 12:43 ` [PATCH v4 03/26] arm64/sysreg: Add SYS_FIELD_GET() helper Mark Brown
2022-06-20 12:43 ` [PATCH v4 04/26] arm64/sysreg: Standardise naming for CTR_EL0 fields Mark Brown
2022-06-20 12:43 ` [PATCH v4 05/26] arm64/sysreg: Standardise naming for DCZID_EL0 field names Mark Brown
2022-06-20 12:43 ` [PATCH v4 06/26] arm64/mte: Standardise GMID field name definitions Mark Brown
2022-06-20 12:43 ` [PATCH v4 07/26] arm64/sysreg: Align pointer auth enumeration defines with architecture Mark Brown
2022-06-20 12:43 ` [PATCH v4 08/26] arm64/sysreg: Make BHB clear feature defines match the architecture Mark Brown
2022-06-20 12:43 ` [PATCH v4 09/26] arm64/sysreg: Standardise naming for WFxT defines Mark Brown
2022-06-20 12:43 ` [PATCH v4 10/26] arm64/sysreg: Standardise naming for ID_AA64SMFR0_EL1 enums Mark Brown
2022-06-20 12:43 ` [PATCH v4 11/26] arm64/sysreg: Standardise naming for ID_AA64ZFR0_EL1 fields Mark Brown
2022-06-20 12:43 ` [PATCH v4 12/26] arm64/sysreg: Remove defines for RPRES enumeration Mark Brown
2022-06-20 12:43 ` [PATCH v4 13/26] arm64/sysreg: Add _EL1 into ID_AA64ISAR1_EL1 definition names Mark Brown
2022-06-20 12:43 ` [PATCH v4 14/26] arm64/sysreg: Add _EL1 into ID_AA64ISAR2_EL1 " Mark Brown
2022-06-20 12:43 ` [PATCH v4 15/26] arm64/sysreg: Convert CTR_EL0 to automatic generation Mark Brown
2022-06-20 12:43 ` [PATCH v4 16/26] arm64/sysreg: Convert DCZID_EL0 " Mark Brown
2022-06-20 12:43 ` [PATCH v4 17/26] arm64/sysreg: Convert GMID " Mark Brown
2022-06-20 12:43 ` [PATCH v4 18/26] arm64/sysreg: Convert ID_AA64ISAR1_EL1 " Mark Brown
2022-06-20 12:44 ` Mark Brown [this message]
2022-06-20 12:44 ` [PATCH v4 20/26] arm64/sysreg: Convert LORSA_EL1 " Mark Brown
2022-06-20 12:44 ` [PATCH v4 21/26] arm64/sysreg: Convert LOREA_EL1 " Mark Brown
2022-06-20 12:44 ` [PATCH v4 22/26] arm64/sysreg: Convert LORN_EL1 " Mark Brown
2022-06-20 12:44 ` [PATCH v4 23/26] arm64/sysreg: Convert LORC_EL1 " Mark Brown
2022-06-20 12:44 ` [PATCH v4 24/26] arm64/sysreg: Convert LORID_EL1 " Mark Brown
2022-06-20 12:44 ` [PATCH v4 25/26] arm64/sysreg: Convert ID_AA64SMFR0_EL1 " Mark Brown
2022-06-20 12:44 ` [PATCH v4 26/26] arm64/sysreg: Convert ID_AA64ZFR0_EL1 " Mark Brown
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