From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
Joey Gouly <joey.gouly@arm.com>,
linux-arm-kernel@lists.infradead.org,
Mark Brown <broonie@kernel.org>
Subject: [PATCH v4 25/26] arm64/sysreg: Convert ID_AA64SMFR0_EL1 to automatic generation
Date: Mon, 20 Jun 2022 13:44:06 +0100 [thread overview]
Message-ID: <20220620124407.482398-26-broonie@kernel.org> (raw)
In-Reply-To: <20220620124407.482398-1-broonie@kernel.org>
Convert ID_AA64SMFR0_EL1 to automatic register generation as per DDI0487H.a,
no functional change.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 18 ----------------
arch/arm64/tools/sysreg | 37 +++++++++++++++++++++++++++++++++
2 files changed, 37 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 6be54e9bdfaf..6496550ec0c0 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -193,7 +193,6 @@
#define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0)
#define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1)
#define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4)
-#define SYS_ID_AA64SMFR0_EL1 sys_reg(3, 0, 0, 4, 5)
#define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0)
#define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1)
@@ -760,23 +759,6 @@
#define ID_AA64ZFR0_EL1_AES_PMULL128 0x2
#define ID_AA64ZFR0_EL1_SVEver_SVE2 0x1
-/* id_aa64smfr0 */
-#define ID_AA64SMFR0_EL1_FA64_SHIFT 63
-#define ID_AA64SMFR0_EL1_I16I64_SHIFT 52
-#define ID_AA64SMFR0_EL1_F64F64_SHIFT 48
-#define ID_AA64SMFR0_EL1_I8I32_SHIFT 36
-#define ID_AA64SMFR0_EL1_F16F32_SHIFT 35
-#define ID_AA64SMFR0_EL1_B16F32_SHIFT 34
-#define ID_AA64SMFR0_EL1_F32F32_SHIFT 32
-
-#define ID_AA64SMFR0_EL1_FA64_IMP 0x1
-#define ID_AA64SMFR0_EL1_I16I64_IMP 0xf
-#define ID_AA64SMFR0_EL1_F64F64_IMP 0x1
-#define ID_AA64SMFR0_EL1_I8I32_IMP 0xf
-#define ID_AA64SMFR0_EL1_F16F32_IMP 0x1
-#define ID_AA64SMFR0_EL1_B16F32_IMP 0x1
-#define ID_AA64SMFR0_EL1_F32F32_IMP 0x1
-
/* id_aa64mmfr0 */
#define ID_AA64MMFR0_ECV_SHIFT 60
#define ID_AA64MMFR0_FGT_SHIFT 56
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index eadf460437d2..d0b34066ce96 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -46,6 +46,43 @@
# feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration
# item ACCDATA) though it may be more taseful to do something else.
+Sysreg ID_AA64SMFR0_EL1 3 0 0 4 5
+Enum 63 FA64
+ 0b0 NI
+ 0b1 IMP
+EndEnum
+Res0 62:60
+Field 59:56 SMEver
+Enum 55:52 I16I64
+ 0b0000 NI
+ 0b1111 IMP
+EndEnum
+Res0 51:49
+Enum 48 F64F64
+ 0b0 NI
+ 0b1 IMP
+EndEnum
+Res0 47:40
+Enum 39:36 I8I32
+ 0b0000 NI
+ 0b1111 IMP
+EndEnum
+Enum 35 F16F32
+ 0b0 NI
+ 0b1 IMP
+EndEnum
+Enum 34 B16F32
+ 0b0 NI
+ 0b1 IMP
+EndEnum
+Res0 33
+Enum 32 F32F32
+ 0b0 NI
+ 0b1 IMP
+EndEnum
+Res0 31:0
+EndSysreg
+
Sysreg ID_AA64ISAR0_EL1 3 0 0 6 0
Enum 63:60 RNDR
0b0000 NI
--
2.30.2
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next prev parent reply other threads:[~2022-06-20 13:09 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-20 12:43 [PATCH v4 00/26] arm64/sysreg: More system register generation Mark Brown
2022-06-20 12:43 ` [PATCH v4 01/26] arm64/cpuinfo: Restore define for AIVIVT cache type Mark Brown
2022-06-22 11:09 ` Mark Rutland
2022-06-22 12:04 ` Mark Brown
2022-06-23 14:08 ` Mark Rutland
2022-06-23 14:30 ` Mark Brown
2022-06-23 14:36 ` Mark Rutland
2022-06-20 12:43 ` [PATCH v4 02/26] arm64/sysreg: Add LINKER_SCRIPT guards for sysreg.h Mark Brown
2022-06-22 11:11 ` Mark Rutland
2022-06-22 11:19 ` Mark Brown
2022-06-22 15:20 ` Mark Rutland
2022-06-20 12:43 ` [PATCH v4 03/26] arm64/sysreg: Add SYS_FIELD_GET() helper Mark Brown
2022-06-20 12:43 ` [PATCH v4 04/26] arm64/sysreg: Standardise naming for CTR_EL0 fields Mark Brown
2022-06-20 12:43 ` [PATCH v4 05/26] arm64/sysreg: Standardise naming for DCZID_EL0 field names Mark Brown
2022-06-20 12:43 ` [PATCH v4 06/26] arm64/mte: Standardise GMID field name definitions Mark Brown
2022-06-20 12:43 ` [PATCH v4 07/26] arm64/sysreg: Align pointer auth enumeration defines with architecture Mark Brown
2022-06-20 12:43 ` [PATCH v4 08/26] arm64/sysreg: Make BHB clear feature defines match the architecture Mark Brown
2022-06-20 12:43 ` [PATCH v4 09/26] arm64/sysreg: Standardise naming for WFxT defines Mark Brown
2022-06-20 12:43 ` [PATCH v4 10/26] arm64/sysreg: Standardise naming for ID_AA64SMFR0_EL1 enums Mark Brown
2022-06-20 12:43 ` [PATCH v4 11/26] arm64/sysreg: Standardise naming for ID_AA64ZFR0_EL1 fields Mark Brown
2022-06-20 12:43 ` [PATCH v4 12/26] arm64/sysreg: Remove defines for RPRES enumeration Mark Brown
2022-06-20 12:43 ` [PATCH v4 13/26] arm64/sysreg: Add _EL1 into ID_AA64ISAR1_EL1 definition names Mark Brown
2022-06-20 12:43 ` [PATCH v4 14/26] arm64/sysreg: Add _EL1 into ID_AA64ISAR2_EL1 " Mark Brown
2022-06-20 12:43 ` [PATCH v4 15/26] arm64/sysreg: Convert CTR_EL0 to automatic generation Mark Brown
2022-06-20 12:43 ` [PATCH v4 16/26] arm64/sysreg: Convert DCZID_EL0 " Mark Brown
2022-06-20 12:43 ` [PATCH v4 17/26] arm64/sysreg: Convert GMID " Mark Brown
2022-06-20 12:43 ` [PATCH v4 18/26] arm64/sysreg: Convert ID_AA64ISAR1_EL1 " Mark Brown
2022-06-20 12:44 ` [PATCH v4 19/26] arm64/sysreg: Convert ID_AA64ISAR2_EL1 " Mark Brown
2022-06-20 12:44 ` [PATCH v4 20/26] arm64/sysreg: Convert LORSA_EL1 " Mark Brown
2022-06-20 12:44 ` [PATCH v4 21/26] arm64/sysreg: Convert LOREA_EL1 " Mark Brown
2022-06-20 12:44 ` [PATCH v4 22/26] arm64/sysreg: Convert LORN_EL1 " Mark Brown
2022-06-20 12:44 ` [PATCH v4 23/26] arm64/sysreg: Convert LORC_EL1 " Mark Brown
2022-06-20 12:44 ` [PATCH v4 24/26] arm64/sysreg: Convert LORID_EL1 " Mark Brown
2022-06-20 12:44 ` Mark Brown [this message]
2022-06-20 12:44 ` [PATCH v4 26/26] arm64/sysreg: Convert ID_AA64ZFR0_EL1 " Mark Brown
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