From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 475C7C43334 for ; Wed, 22 Jun 2022 18:00:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=SMTWwlZw2n/O52NSI6dDTd4hTLZ+3p3uidtYBCZ4Qpk=; b=Q6TOLSQZ9+iboE duPL8sd0B+3gzWaNXWI4iR4cDrq2xSkAF8ZlpriiNTCFnKiuVXcwifmnBPNM3nfdX1Q2j5aydoVf2 +7PacDDkEpFcwtx092LsZYe9raNsNhu38wzTIJ+oBumhejaJDPMhqpRty7FLZVm68iXScOpVWVKzL 1PCrJbGC/y2jmwdRW+uxYWI8IBMQn8Hp/HFmyIQBRCjBn81nxn9B5tWTUyfRxBadvz88/I0UtTBR/ FJrxPo6/Xx0/Tmhmz2yOGquQw9EGCn34bTo7zsSdJbx9PUd3S+pAhigjyYUNVPT+Z/W1rhDCSfvFn A2hzQAvA6IZppTOjCT9w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o44dY-00BoNS-H2; Wed, 22 Jun 2022 17:59:32 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o44XV-00BlcC-E8 for linux-arm-kernel@lists.infradead.org; Wed, 22 Jun 2022 17:53:20 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 0F066B82076; Wed, 22 Jun 2022 17:53:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6B455C3411D; Wed, 22 Jun 2022 17:53:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655920394; bh=M/C0f7QFe7fvshqOippHw0Unx9VEAZ/cIw3cWYYe6/4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I9Ernh9CH6AXFiS3tmC1dYrfKX2AbRUQmuydCpKHB9nT96WemZAdbpZ3EnCw9/0Wz fvX5aAwXVpFP/JuCnZA2ZCP22GFPGSKFtPg69FlEyZtn5VfMhIWAbnwISJFBvws9UM AQ0L6HlL4qbMk+9qbbxBSe2T5TU2wdvJIY5NsZpAo08wQqJZYshNzWXntyBvx6jWw/ Nu7PWyWyXVsd2PIML1syloBt6l1T5ReK6S1dmyJh//vuabqrnMzkBw3ms9cIRKQ5Q8 ylws+/bbeyH4/rrvEKV9PyK2a3QtBZvuYssyHgtEl5DCFb+MjpNmslXm7yOMMsT/XU Cqkzz+bUWVahQ== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v5 15/27] arm64/sysreg: Add _EL1 into ID_AA64ISAR2_EL1 definition names Date: Wed, 22 Jun 2022 18:44:04 +0100 Message-Id: <20220622174416.1406282-16-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220622174416.1406282-1-broonie@kernel.org> References: <20220622174416.1406282-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=11160; h=from:subject; bh=M/C0f7QFe7fvshqOippHw0Unx9VEAZ/cIw3cWYYe6/4=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBis1Tl1BvEDIWYirPaF9tdhbysXs1E+MVqrEBQxLRf SEisc5OJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYrNU5QAKCRAk1otyXVSH0MNbB/ 4zWKAxaPW9hG+z4Mf1WpIFkoIwDmUAHjsEwj+p/2pU4cmKLkZNTW0u2IrQey4jIn2P+TTsX3nDGroC PRk1Qzz1MjcIhemVPabzmgDQjvbd3yO4mtkls18dxfoMyZn88JqmMk5rwVnsbeF7xdEWOThnJdNs5v Zsp6epiqoM0epQkAzL1+IQkBPdmNKTdECSon7IRDELyl5UroBJHvLtqKLfaJE7Y7mys3oyuZ6Md7hg GW+vOgG/Qp5xAfLINujbHcs4jrgynj+Ul0rfQPBoUL6dgCmPb88t6kh4EcAt5F3xDUWGzXx49k6iLX 1eyc4LlkHob5aZe2zhnW4y68r4m3qt X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220622_105317_849206_A9B8E224 X-CRM114-Status: GOOD ( 21.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Normally we include the full register name in the defines for fields within registers but this has not been followed for ID registers. In preparation for automatic generation of defines add the _EL1s into the defines for ID_AA64ISAR2_EL1 to follow the convention. No functional changes. Signed-off-by: Mark Brown --- arch/arm64/include/asm/asm_pointer_auth.h | 2 +- arch/arm64/include/asm/cpufeature.h | 2 +- arch/arm64/include/asm/sysreg.h | 34 +++++++++---------- arch/arm64/kernel/cpufeature.c | 34 +++++++++---------- arch/arm64/kernel/idreg-override.c | 4 +-- .../arm64/kvm/hyp/include/nvhe/fixed_config.h | 4 +-- arch/arm64/kvm/hyp/nvhe/sys_regs.c | 4 +-- arch/arm64/kvm/sys_regs.c | 6 ++-- 8 files changed, 45 insertions(+), 45 deletions(-) diff --git a/arch/arm64/include/asm/asm_pointer_auth.h b/arch/arm64/include/asm/asm_pointer_auth.h index 3b192e04a5dd..13ecc79854ee 100644 --- a/arch/arm64/include/asm/asm_pointer_auth.h +++ b/arch/arm64/include/asm/asm_pointer_auth.h @@ -61,7 +61,7 @@ alternative_else_nop_endif mrs \tmp1, id_aa64isar1_el1 ubfx \tmp1, \tmp1, #ID_AA64ISAR1_EL1_APA_SHIFT, #8 mrs_s \tmp2, SYS_ID_AA64ISAR2_EL1 - ubfx \tmp2, \tmp2, #ID_AA64ISAR2_APA3_SHIFT, #4 + ubfx \tmp2, \tmp2, #ID_AA64ISAR2_EL1_APA3_SHIFT, #4 orr \tmp1, \tmp1, \tmp2 cbz \tmp1, .Lno_addr_auth\@ mov_q \tmp1, (SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | \ diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 6472f2badc97..fe59035bdc22 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -673,7 +673,7 @@ static inline bool supports_clearbhb(int scope) isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1); return cpuid_feature_extract_unsigned_field(isar2, - ID_AA64ISAR2_BC_SHIFT); + ID_AA64ISAR2_EL1_BC_SHIFT); } const struct cpumask *system_32bit_el0_cpumask(void); diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index ba9053bc33c2..7f083a2ed7dc 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -738,29 +738,29 @@ #define ID_AA64ISAR1_EL1_GPI_IMP 0x1 /* id_aa64isar2 */ -#define ID_AA64ISAR2_BC_SHIFT 28 -#define ID_AA64ISAR2_APA3_SHIFT 12 -#define ID_AA64ISAR2_GPA3_SHIFT 8 -#define ID_AA64ISAR2_RPRES_SHIFT 4 -#define ID_AA64ISAR2_WFxT_SHIFT 0 +#define ID_AA64ISAR2_EL1_BC_SHIFT 28 +#define ID_AA64ISAR2_EL1_APA3_SHIFT 12 +#define ID_AA64ISAR2_EL1_GPA3_SHIFT 8 +#define ID_AA64ISAR2_EL1_RPRES_SHIFT 4 +#define ID_AA64ISAR2_EL1_WFxT_SHIFT 0 /* * Value 0x1 has been removed from the architecture, and is * reserved, but has not yet been removed from the ARM ARM * as of ARM DDI 0487G.b. */ -#define ID_AA64ISAR2_WFxT_NI 0x0 -#define ID_AA64ISAR2_WFxT_IMP 0x2 - -#define ID_AA64ISAR2_APA3_NI 0x0 -#define ID_AA64ISAR2_APA3_PAuth 0x1 -#define ID_AA64ISAR2_APA3_EPAC 0x2 -#define ID_AA64ISAR2_APA3_PAuth2 0x3 -#define ID_AA64ISAR2_APA3_FPAC 0x4 -#define ID_AA64ISAR2_APA3_FPACCOMBINE 0x5 - -#define ID_AA64ISAR2_GPA3_NI 0x0 -#define ID_AA64ISAR2_GPA3_IMP 0x1 +#define ID_AA64ISAR2_EL1_WFxT_NI 0x0 +#define ID_AA64ISAR2_EL1_WFxT_IMP 0x2 + +#define ID_AA64ISAR2_EL1_APA3_NI 0x0 +#define ID_AA64ISAR2_EL1_APA3_PAuth 0x1 +#define ID_AA64ISAR2_EL1_APA3_EPAC 0x2 +#define ID_AA64ISAR2_EL1_APA3_PAuth2 0x3 +#define ID_AA64ISAR2_EL1_APA3_FPAC 0x4 +#define ID_AA64ISAR2_EL1_APA3_FPACCOMBINE 0x5 + +#define ID_AA64ISAR2_EL1_GPA3_NI 0x0 +#define ID_AA64ISAR2_EL1_GPA3_IMP 0x1 /* id_aa64pfr0 */ #define ID_AA64PFR0_CSV3_SHIFT 60 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 0d4f0120c516..be20100a7d4c 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -231,13 +231,13 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { }; static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_BC_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), - FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_APA3_SHIFT, 4, 0), + FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_GPA3_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_RPRES_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_WFxT_SHIFT, 4, 0), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), ARM64_FTR_END, }; @@ -2326,9 +2326,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, .sys_reg = SYS_ID_AA64ISAR2_EL1, .sign = FTR_UNSIGNED, - .field_pos = ID_AA64ISAR2_APA3_SHIFT, + .field_pos = ID_AA64ISAR2_EL1_APA3_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR2_APA3_PAuth, + .min_field_value = ID_AA64ISAR2_EL1_APA3_PAuth, .matches = has_address_auth_cpucap, }, { @@ -2364,9 +2364,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_SYSTEM_FEATURE, .sys_reg = SYS_ID_AA64ISAR2_EL1, .sign = FTR_UNSIGNED, - .field_pos = ID_AA64ISAR2_GPA3_SHIFT, + .field_pos = ID_AA64ISAR2_EL1_GPA3_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR2_GPA3_IMP, + .min_field_value = ID_AA64ISAR2_EL1_GPA3_IMP, .matches = has_cpuid_feature, }, { @@ -2516,10 +2516,10 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_SYSTEM_FEATURE, .sys_reg = SYS_ID_AA64ISAR2_EL1, .sign = FTR_UNSIGNED, - .field_pos = ID_AA64ISAR2_WFxT_SHIFT, + .field_pos = ID_AA64ISAR2_EL1_WFxT_SHIFT, .field_width = 4, .matches = has_cpuid_feature, - .min_field_value = ID_AA64ISAR2_WFxT_IMP, + .min_field_value = ID_AA64ISAR2_EL1_WFxT_IMP, }, {}, }; @@ -2565,8 +2565,8 @@ static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { ID_AA64ISAR1_EL1_APA_PAuth) }, { - HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_APA3_SHIFT, - 4, FTR_UNSIGNED, ID_AA64ISAR2_APA3_PAuth) + HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_APA3_SHIFT, + 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_APA3_PAuth) }, { HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_API_SHIFT, @@ -2581,8 +2581,8 @@ static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPA_IMP) }, { - HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_GPA3_SHIFT, - 4, FTR_UNSIGNED, ID_AA64ISAR2_GPA3_IMP) + HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_GPA3_SHIFT, + 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_GPA3_IMP) }, { HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPI_SHIFT, @@ -2653,8 +2653,8 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { #endif /* CONFIG_ARM64_MTE */ HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV), HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP), - HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES), - HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), + HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES), + HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), #ifdef CONFIG_ARM64_SME HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SME, CAP_HWCAP, KERNEL_HWCAP_SME), HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_FA64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), diff --git a/arch/arm64/kernel/idreg-override.c b/arch/arm64/kernel/idreg-override.c index 652c19b13588..720a847f7dfe 100644 --- a/arch/arm64/kernel/idreg-override.c +++ b/arch/arm64/kernel/idreg-override.c @@ -75,8 +75,8 @@ static const struct ftr_set_desc isar2 __initconst = { .name = "id_aa64isar2", .override = &id_aa64isar2_override, .fields = { - { "gpa3", ID_AA64ISAR2_GPA3_SHIFT }, - { "apa3", ID_AA64ISAR2_APA3_SHIFT }, + { "gpa3", ID_AA64ISAR2_EL1_GPA3_SHIFT }, + { "apa3", ID_AA64ISAR2_EL1_APA3_SHIFT }, {} }, }; diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h index 46cf9dec21ba..fa6e466ed57f 100644 --- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h +++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h @@ -193,8 +193,8 @@ ) #define PVM_ID_AA64ISAR2_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64ISAR2_GPA3) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR2_APA3) \ + ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) \ ) u64 pvm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id); diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/sys_regs.c index 5b77bc1cca0c..6b94c3e6ff26 100644 --- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c +++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c @@ -186,8 +186,8 @@ static u64 get_pvm_id_aa64isar2(const struct kvm_vcpu *vcpu) u64 allow_mask = PVM_ID_AA64ISAR2_ALLOW; if (!vcpu_has_ptrauth(vcpu)) - allow_mask &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_APA3) | - ARM64_FEATURE_MASK(ID_AA64ISAR2_GPA3)); + allow_mask &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | + ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); return id_aa64isar2_el1_sys_val & allow_mask; } diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index ccd973dc346a..c4fb3874b5e2 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1143,10 +1143,10 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, break; case SYS_ID_AA64ISAR2_EL1: if (!vcpu_has_ptrauth(vcpu)) - val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_APA3) | - ARM64_FEATURE_MASK(ID_AA64ISAR2_GPA3)); + val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | + ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); if (!cpus_have_final_cap(ARM64_HAS_WFXT)) - val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_WFxT); + val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); break; case SYS_ID_AA64DFR0_EL1: /* Limit debug to ARMv8.0 */ -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel