From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5BCEBC43334 for ; Sat, 25 Jun 2022 05:40:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=JprolHdJfRGN9/fYY1rHpkHiXl5sv3WxMURv14mBIwk=; b=G+OnCfJpUyQGe/ c/C5u+bspQ/UFlXpOs8GjVyARW25PNYKQ7CJiXOhjOnSReGl7un+xWlgWsKm+0t/ywl4Kg/BmB7j3 5bB+6jj7Kt9ff84m5sBSTAx/TBqUrto4/Vm6phdRVj95OB91FEVo6I2Jiv5EQup7wwpgOdF3tcafb /hcR7EA4H5569Fzs1ScrbPzGM0PGLqbAj7rh0SF+CZ54biwOzlTd+RLKrAigVAbMYFmMG3FS0zAWj aL012bbOdVRWwUd1KGUw14VW4106KqrJt41XoMrC+LdOYy6pQR9LUNEvfm3ilT8GU0S7AwjxZTfhH HZwzUTJi2zF1mYOtewTg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o4yW0-004jg1-2O; Sat, 25 Jun 2022 05:39:28 +0000 Received: from forward500j.mail.yandex.net ([5.45.198.250]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o4yVv-004jea-LA; Sat, 25 Jun 2022 05:39:25 +0000 Received: from iva1-5d4bed9ec33e.qloud-c.yandex.net (iva1-5d4bed9ec33e.qloud-c.yandex.net [IPv6:2a02:6b8:c0c:298:0:640:5d4b:ed9e]) by forward500j.mail.yandex.net (Yandex) with ESMTP id 2E2AA6CB8553; Sat, 25 Jun 2022 08:39:21 +0300 (MSK) Received: from iva6-2d18925256a6.qloud-c.yandex.net (iva6-2d18925256a6.qloud-c.yandex.net [2a02:6b8:c0c:7594:0:640:2d18:9252]) by iva1-5d4bed9ec33e.qloud-c.yandex.net (mxback/Yandex) with ESMTP id 6mNwP7t9KO-dJfSARhe; Sat, 25 Jun 2022 08:39:21 +0300 X-Yandex-Fwd: 2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1656135561; bh=sO6lv1ZaVsGCGLQcMcTq6F56qYmSsejjTXP/P42zzXY=; h=In-Reply-To:Subject:Cc:To:From:References:Date:Message-ID; b=o5oyqrUGzYOQV9pIoheCfiSYg/iYp5RNTfmP5Rqp6hyA0t2jBZUjqDsLrpwofU/i+ eT+y4CEGRYKpEvQ+C4PmFKo3hxCJ4qhe5/KbXXbuz3R4uL4axfkLIoroPBsNLsXg5O GeOELEHAjAXBeCZ8qbTccK8xNPq6vUqHQfcKiAiE= Authentication-Results: iva1-5d4bed9ec33e.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me Received: by iva6-2d18925256a6.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id FJ8J2gkSvz-dHMu2Cgc; Sat, 25 Jun 2022 08:39:18 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) Date: Sat, 25 Jun 2022 08:39:16 +0300 From: Nikita Shubin To: Atish Patra Cc: Anup Patel , =?UTF-8?B?Sm/Do28gTcOhcmlv?= Domingos , linux , Nikita Shubin , Albert Ou , Alexander Shishkin , Arnaldo Carvalho de Melo , Ingo Molnar , Jiri Olsa , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org List" , linux-perf-users@vger.kernel.org, linux-riscv , Mark Rutland , Namhyung Kim , Palmer Dabbelt , Paul Walmsley , Peter Zijlstra , Will Deacon Subject: Re: [PATCH v4 0/5] RISC-V: Create unique identification for SoC PMU Message-ID: <20220625083916.66e75def@redslave.neermore.group> In-Reply-To: References: <20220624160117.3206-1-nikita.shubin@maquefel.me> X-Mailer: Claws Mail 3.17.7 (GTK+ 2.24.33; x86_64-pc-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220624_223924_122879_02028C83 X-CRM114-Status: GOOD ( 25.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello Atish! On Fri, 24 Jun 2022 10:05:34 -0700 Atish Patra wrote: > On Fri, Jun 24, 2022 at 9:01 AM Nikita Shubin > wrote: > > > > From: Nikita Shubin > > > > This series aims to provide matching vendor SoC with corresponded > > JSON bindings. > > > > The ID string is proposed to be in form of > > MVENDORID-MARCHID-MIMPID, for example for Sifive Unmatched the > > corresponding string will be: > > > > 0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core > > > > Where MIMPID can vary as all impl supported the same number of > > events, this might not be true for all future SoC however. > > > > Also added 3 counters which are standart for all RISC-V > > implementations and SBI firmware events prerry names, as any > > firmware that supports SBI PMU should also support firmare events. > > > > Link: > > https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc > > Link: > > https://patchwork.kernel.org/project/linux-riscv/list/?series=648017 > > --- v3->v4: > > - drop pmuid in riscv_pmu_sbi, we are using /proc/cpuinfo > > - rework util/header.c to use /proc/cpuinfo > > - add SBI firmware events > > - add firmware and std arch events to U74 pmu bindings > > - change U74 id string and description in mapfile.csv > > --- > > Nikita Shubin (5): > > drivers/perf: riscv_pmu_sbi: perf format > > perf tools riscv: Add support for get_cpuid_str function > > perf arch events: riscv arch std event files > > perf arch events: riscv sbi firmare std event files > > perf vendor events riscv: add Sifive U74 JSON file > > > > drivers/perf/riscv_pmu_sbi.c | 20 +++ > > tools/perf/arch/riscv/util/Build | 1 + > > tools/perf/arch/riscv/util/header.c | 109 ++++++++++++++ > > tools/perf/pmu-events/arch/riscv/mapfile.csv | 17 +++ > > .../pmu-events/arch/riscv/riscv-generic.json | 20 +++ > > .../arch/riscv/riscv-sbi-firmware.json | 134 > > ++++++++++++++++++ .../arch/riscv/sifive/u74/firmware.json | > > 68 +++++++++ .../arch/riscv/sifive/u74/generic.json | 11 ++ > > .../arch/riscv/sifive/u74/instructions.json | 92 ++++++++++++ > > .../arch/riscv/sifive/u74/memory.json | 32 +++++ > > .../arch/riscv/sifive/u74/microarch.json | 57 ++++++++ > > 11 files changed, 561 insertions(+) > > create mode 100644 tools/perf/arch/riscv/util/header.c > > create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv > > create mode 100644 > > tools/perf/pmu-events/arch/riscv/riscv-generic.json create mode > > 100644 tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json > > create mode 100644 > > tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json create > > mode 100644 > > tools/perf/pmu-events/arch/riscv/sifive/u74/generic.json create > > mode 100644 > > tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json > > create mode 100644 > > tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json create mode > > 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json > > > > -- > > 2.35.1 > > > > Thanks Nikita for reworking on the patches. It is good to specify that > this series now depends > on Anup's patch[1] that adds the mvendorid/mimpid to the > /proc/cpuinfo. > > [1] https://lkml.org/lkml/2022/6/20/498 > I will correct the remarks and fire a v5 next week then, hope some more comments will rise for current version. Do you have any thoughts or comments on cpuid form "MVENDORID-MARCHID-MIMPID" ? _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel