From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B2136C43334 for ; Tue, 28 Jun 2022 14:27:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=SVTYWx6eDqSi6f8kt4I621H8u4LlAJJJWK+6U11ZmT8=; b=dS5S3nlIxSGqLF lNibvO6kIqqfMvE2rDsW7RHedD3CCxmKXijVA4hr19Aur1R7SmLwjSQpyCS67gOnP9vxeEFy1eriP pdMzJLAwctqv8GSGBoThqP/IMnt6G5m1fhBABFRCe0etEOP6nG+HDkUmE1XgxM2IvuZSTGokX0F72 JStl6J814n6LHsJxD2hDptNTOZ3rwmU3LaQnzQ9RolNWBrPDU35NGaVrFHLDcA5fdCBUirZqjYxZx dcZpnBjZ7HtFh7P4DO01IIeGhnz3cflRB3fTnVGvkpgVHMXXvrbZWfKiCTfxk6SmoHkncNuSAWjE4 zzJ+L2In4OXEnHDS3DWw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o6CAS-006hxq-Ah; Tue, 28 Jun 2022 14:26:16 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o6CAO-006hwr-5R for linux-arm-kernel@lists.infradead.org; Tue, 28 Jun 2022 14:26:15 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 83D6561AC7; Tue, 28 Jun 2022 14:26:11 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D754EC3411D; Tue, 28 Jun 2022 14:26:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656426370; bh=URQiVmB69UNPufuwtnG+lMs8IHi8tIb6do79p7ogUIY=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=assAdTsycKSNjs/pOhCnIrCeLzMWJmD0sgBlra/dkTklq1PVlFH3v/14BgFBsijFo 0/AY9R7PNEBIl4uucZBL7R+0m87p6cEp6gA+7Gn7xLxt2vzsFzP3N1HYiH3VoWkaK8 g+JsyQtDxPJ5o6KjYphpC8+lKU6MHbgmc6Wq/EmfteI6WCx0IwmXUJcqvnEcoBVG4H RjWtK/M3Jg+95yDBilpbeayZ2Euz7ekPPu7FkXeYkSnhMRSiJs64mey3G70VYMnA6a 5unlh9T4rfyTf6dBOPWORiiML6sEsR5sHnm/VNRHJG3xgO1rC0nuH5in+WrkthkJQR cN60quYCCk2ng== Date: Tue, 28 Jun 2022 15:26:06 +0100 From: Will Deacon To: Mark Brown Cc: Catalin Marinas , Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v5 01/27] arm64/cpuinfo: Remove refrences to reserved cache type Message-ID: <20220628142605.GC24116@willie-the-truck> References: <20220622174416.1406282-1-broonie@kernel.org> <20220622174416.1406282-2-broonie@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220622174416.1406282-2-broonie@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220628_072612_335739_5B7F051B X-CRM114-Status: GOOD ( 26.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jun 22, 2022 at 06:43:50PM +0100, Mark Brown wrote: > In 155433cb365ee466 ("arm64: cache: Remove support for ASID-tagged VIVT > I-caches") we removed all the support fir AIVIVT cache types and renamed s/fir/for/ > all references to the field to say "unknown" since support for AIVIVT > caches was removed from the architecture. Some confusion has resulted since > the corresponding change to the architecture left the value named as > AIVIVT but documented it as reserved in v8, refactor the code so we don't > define the constant instead. This will help with automatic generation of > this register field since it means we care less about the correspondence > with the ARM. > > No functional change, the value displayed to userspace is unchanged. > > Signed-off-by: Mark Brown > --- > arch/arm64/include/asm/cache.h | 1 - > arch/arm64/kernel/cpuinfo.c | 27 +++++++++++++++++---------- > 2 files changed, 17 insertions(+), 11 deletions(-) > > diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h > index 7c2181c72116..0cbe75b9e4e5 100644 > --- a/arch/arm64/include/asm/cache.h > +++ b/arch/arm64/include/asm/cache.h > @@ -25,7 +25,6 @@ > #define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK) > > #define ICACHE_POLICY_VPIPT 0 > -#define ICACHE_POLICY_RESERVED 1 > #define ICACHE_POLICY_VIPT 2 > #define ICACHE_POLICY_PIPT 3 > > diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c > index 8eff0a34ffd4..7ecf9ffb590b 100644 > --- a/arch/arm64/kernel/cpuinfo.c > +++ b/arch/arm64/kernel/cpuinfo.c > @@ -33,12 +33,19 @@ > DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data); > static struct cpuinfo_arm64 boot_cpu_data; > > -static const char *icache_policy_str[] = { > - [ICACHE_POLICY_VPIPT] = "VPIPT", > - [ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN", > - [ICACHE_POLICY_VIPT] = "VIPT", > - [ICACHE_POLICY_PIPT] = "PIPT", > -}; > +static inline const char *icache_policy_str(int l1ip) > +{ > + switch (l1ip) { > + case ICACHE_POLICY_VPIPT: > + return "VPIPT"; > + case ICACHE_POLICY_VIPT: > + return "VIPT"; > + case ICACHE_POLICY_PIPT: > + return "PIPT"; > + default: > + return "RESERVED/UNKNOWN"; > + } Looks like the indentation has gone wonky here. > unsigned long __icache_flags; > > @@ -342,19 +349,19 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) > u32 l1ip = CTR_L1IP(info->reg_ctr); > > switch (l1ip) { > - case ICACHE_POLICY_PIPT: > - break; > case ICACHE_POLICY_VPIPT: > set_bit(ICACHEF_VPIPT, &__icache_flags); > break; > - case ICACHE_POLICY_RESERVED: > case ICACHE_POLICY_VIPT: > /* Assume aliasing */ > set_bit(ICACHEF_ALIASING, &__icache_flags); > break; Shouldn't we still assume aliasing if we see an I-cache that we don't know about? Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel