From: Stephen Boyd <sboyd@kernel.org>
To: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>,
Jakub Kicinski <kuba@kernel.org>,
Jonathan Lemon <jonathan.lemon@gmail.com>,
Vadim Fedorenko <vfedorenko@novek.ru>
Cc: Vadim Fedorenko <vadfed@fb.com>, Aya Levin <ayal@nvidia.com>,
netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-clk@vger.kernel.org
Subject: Re: [RFC PATCH v2 1/3] dpll: Add DPLL framework base functions
Date: Wed, 29 Jun 2022 01:34:37 -0700 [thread overview]
Message-ID: <20220629083439.6F5E3C34114@smtp.kernel.org> (raw)
In-Reply-To: <20220626192444.29321-2-vfedorenko@novek.ru>
Quoting Vadim Fedorenko (2022-06-26 12:24:42)
> From: Vadim Fedorenko <vadfed@fb.com>
>
> DPLL framework is used to represent and configure DPLL devices
> in systems. Each device that has DPLL and can configure sources
> and outputs can use this framework.
Please add more details to the commit text, and possibly introduce some
Documentation/ about this driver subsystem. I'm curious what is
different from drivers/clk/, is it super large frequencies that don't
fit into 32-bits when represented in Hz? Or PLL focused? Or is sub-Hz
required?
Details please!
Does DPLL stand for digital phase locked loop? Again, I have no idea! I
think you get my point.
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next prev parent reply other threads:[~2022-06-29 8:35 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-26 19:24 [RFC PATCH v2 0/3] Create common DPLL/clock configuration API Vadim Fedorenko
2022-06-26 19:24 ` [RFC PATCH v2 1/3] dpll: Add DPLL framework base functions Vadim Fedorenko
2022-06-29 8:34 ` Stephen Boyd [this message]
2022-06-29 23:37 ` Vadim Fedorenko
2022-07-11 9:01 ` Kubalewski, Arkadiusz
2022-07-14 23:23 ` Vadim Fedorenko
2022-07-15 17:31 ` Kubalewski, Arkadiusz
2022-06-26 19:24 ` [RFC PATCH v2 2/3] dpll: add netlink events Vadim Fedorenko
2022-07-11 9:02 ` Kubalewski, Arkadiusz
2022-07-14 23:29 ` Vadim Fedorenko
2022-07-15 17:31 ` Kubalewski, Arkadiusz
2022-08-02 14:02 ` Kubalewski, Arkadiusz
2022-08-02 15:52 ` Jakub Kicinski
2022-08-03 0:05 ` Vadim Fedorenko
2022-08-03 15:21 ` Stephen Hemminger
2022-09-29 12:13 ` Jiri Pirko
2022-09-30 0:48 ` Vadim Fedorenko
2022-06-26 19:24 ` [RFC PATCH v2 3/3] ptp_ocp: implement DPLL ops Vadim Fedorenko
2022-06-27 19:34 ` Jonathan Lemon
2022-06-27 22:13 ` Vadim Fedorenko
2022-06-28 19:11 ` Jonathan Lemon
2022-06-29 3:24 ` Jakub Kicinski
2022-06-29 23:31 ` Vadim Fedorenko
2022-09-29 11:33 ` Jiri Pirko
2022-09-30 0:56 ` Vadim Fedorenko
2022-09-01 12:02 ` [RFC PATCH v2 0/3] Create common DPLL/clock configuration API Gal Pressman
2022-09-29 11:40 ` Jiri Pirko
2022-09-30 0:44 ` Vadim Fedorenko
2022-09-30 8:33 ` Jiri Pirko
2022-09-30 14:33 ` Jakub Kicinski
2022-10-01 5:47 ` Jiri Pirko
2022-10-01 14:18 ` Jakub Kicinski
2022-10-02 14:35 ` Jiri Pirko
2022-10-03 14:28 ` Jakub Kicinski
2022-10-03 17:20 ` Vadim Fedorenko
2022-10-04 6:33 ` Jiri Pirko
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