From: Ard Biesheuvel <ardb@kernel.org>
To: linux-arm-kernel@lists.infradead.org
Cc: "Ard Biesheuvel" <ardb@kernel.org>,
"Will Deacon" <will@kernel.org>, "Marc Zyngier" <maz@kernel.org>,
"Pierre-Clément Tosi" <ptosi@google.com>,
"Quentin Perret" <qperret@google.com>,
"Mark Rutland" <mark.rutland@arm.com>
Subject: [PATCH 5/6] arm64: head: clean the ID map page to the PoC
Date: Thu, 30 Jun 2022 16:42:29 +0200 [thread overview]
Message-ID: <20220630144230.2332555-6-ardb@kernel.org> (raw)
In-Reply-To: <20220630144230.2332555-1-ardb@kernel.org>
If we enter with the MMU and caches enabled, the caller may not have
performed any cache maintenance. So clean the ID mapped page to the PoC,
to ensure that instruction and data accesses with the MMU off see the
correct data.
Note that this means primary_entry() itself needs to be moved into the
ID map as well, as we will return from init_kernel_el() with the MMU and
caches off.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
arch/arm64/kernel/head.S | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 42fc7e980b35..4ca4d66b418f 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -70,7 +70,7 @@
__EFI_PE_HEADER
- __INIT
+ .section ".idmap.text","awx"
/*
* The following callee saved general purpose registers are used on the
@@ -89,6 +89,17 @@ SYM_CODE_START(primary_entry)
bl record_mmu_state
bl preserve_boot_args
bl create_idmap
+
+ /*
+ * If we entered with the MMU and caches on, clean the ID mapped part
+ * of the primary boot code to the PoC so we can safely execute it with
+ * the MMU off.
+ */
+ cbz x19, 0f
+ adrp x0, __idmap_text_start
+ adr_l x1, __idmap_text_end
+ bl dcache_clean_poc
+0:
bl init_kernel_el // w0=cpu_boot_mode
mov x20, x0
@@ -109,6 +120,7 @@ SYM_CODE_START(primary_entry)
b __primary_switch
SYM_CODE_END(primary_entry)
+ __INIT
SYM_CODE_START_LOCAL(record_mmu_state)
mrs x19, CurrentEL
cmp x19, #CurrentEL_EL2
--
2.35.1
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next prev parent reply other threads:[~2022-06-30 14:45 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-30 14:42 [PATCH 0/6] arm64: efi: boot with MMU and caches on if possible Ard Biesheuvel
2022-06-30 14:42 ` [PATCH 1/6] arm64: lds: reduce effective minimum image alignment to 64k Ard Biesheuvel
2022-06-30 14:42 ` [PATCH 2/6] arm64: kernel: move ID map out of .text mapping Ard Biesheuvel
2022-06-30 14:42 ` [PATCH 3/6] arm64: head: record the MMU state at primary entry Ard Biesheuvel
2022-06-30 14:42 ` [PATCH 4/6] arm64: head: avoid cache invalidation when entering with the MMU on Ard Biesheuvel
2022-06-30 14:42 ` Ard Biesheuvel [this message]
2022-06-30 14:42 ` [PATCH 6/6] arm64: efi/libstub: enter with the MMU on if executing in place Ard Biesheuvel
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