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From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
	Joey Gouly <joey.gouly@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	Mark Brown <broonie@kernel.org>
Subject: [PATCH v7 28/28] arm64/sysreg: Convert ID_AA64ZFR0_EL1 to automatic generation
Date: Mon,  4 Jul 2022 18:03:02 +0100	[thread overview]
Message-ID: <20220704170302.2609529-29-broonie@kernel.org> (raw)
In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org>

Convert ID_AA64ZFR0_EL1 to automatic register generation as per DDI0487H.a,
no functional changes.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/sysreg.h | 23 -----------------
 arch/arm64/tools/sysreg         | 46 +++++++++++++++++++++++++++++++++
 2 files changed, 46 insertions(+), 23 deletions(-)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 2e2b5811e081..d7f115368197 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -192,7 +192,6 @@
 
 #define SYS_ID_AA64PFR0_EL1		sys_reg(3, 0, 0, 4, 0)
 #define SYS_ID_AA64PFR1_EL1		sys_reg(3, 0, 0, 4, 1)
-#define SYS_ID_AA64ZFR0_EL1		sys_reg(3, 0, 0, 4, 4)
 
 #define SYS_ID_AA64DFR0_EL1		sys_reg(3, 0, 0, 5, 0)
 #define SYS_ID_AA64DFR1_EL1		sys_reg(3, 0, 0, 5, 1)
@@ -737,28 +736,6 @@
 #define ID_AA64PFR1_MTE			0x2
 #define ID_AA64PFR1_MTE_ASYMM		0x3
 
-/* id_aa64zfr0 */
-#define ID_AA64ZFR0_EL1_F64MM_SHIFT	56
-#define ID_AA64ZFR0_EL1_F32MM_SHIFT	52
-#define ID_AA64ZFR0_EL1_I8MM_SHIFT	44
-#define ID_AA64ZFR0_EL1_SM4_SHIFT	40
-#define ID_AA64ZFR0_EL1_SHA3_SHIFT	32
-#define ID_AA64ZFR0_EL1_BF16_SHIFT	20
-#define ID_AA64ZFR0_EL1_BitPerm_SHIFT	16
-#define ID_AA64ZFR0_EL1_AES_SHIFT	4
-#define ID_AA64ZFR0_EL1_SVEver_SHIFT	0
-
-#define ID_AA64ZFR0_EL1_F64MM_IMP	0x1
-#define ID_AA64ZFR0_EL1_F32MM_IMP	0x1
-#define ID_AA64ZFR0_EL1_I8MM_IMP	0x1
-#define ID_AA64ZFR0_EL1_BF16_IMP	0x1
-#define ID_AA64ZFR0_EL1_SM4_IMP		0x1
-#define ID_AA64ZFR0_EL1_SHA3_IMP	0x1
-#define ID_AA64ZFR0_EL1_BitPerm_IMP	0x1
-#define ID_AA64ZFR0_EL1_AES_IMP		0x1
-#define ID_AA64ZFR0_EL1_AES_PMULL128	0x2
-#define ID_AA64ZFR0_EL1_SVEver_SVE2	0x1
-
 /* id_aa64mmfr0 */
 #define ID_AA64MMFR0_ECV_SHIFT		60
 #define ID_AA64MMFR0_FGT_SHIFT		56
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index b5c4251c6796..9ae483ec1e56 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -46,6 +46,52 @@
 # feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration
 # item ACCDATA) though it may be more taseful to do something else.
 
+Sysreg	ID_AA64ZFR0_EL1	3	0	0	4	4
+Res0	63:60
+Enum	59:56	F64MM
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	55:52	F32MM
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Res0	51:48
+Enum	47:44	I8MM
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	43:40	SM4
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Res0	39:36
+Enum	35:32	SHA3
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Res0	31:24
+Enum	23:20	BF16
+	0b0000	NI
+	0b0001	IMP
+	0b0010	EBF16
+EndEnum
+Enum	19:16	BitPerm
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Res0	15:8
+Enum	7:4	AES
+	0b0000	NI
+	0b0001	IMP
+	0b0010	PMULL128
+EndEnum
+Enum	3:0	SVEver
+	0b0000	IMP
+	0b0001	SVE2
+EndEnum
+EndSysreg
+
 Sysreg	ID_AA64SMFR0_EL1	3	0	0	4	5
 Enum	63	FA64
 	0b0	NI
-- 
2.30.2


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  parent reply	other threads:[~2022-07-04 17:22 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-04 17:02 [PATCH v7 00/28] arm64/sysreg: More system register generation Mark Brown
2022-07-04 17:02 ` [PATCH v7 01/28] arm64/cpuinfo: Remove references to reserved cache type Mark Brown
2022-07-04 17:02 ` [PATCH v7 02/28] arm64/idreg: Fix tab/space damage Mark Brown
2022-07-04 17:02 ` [PATCH v7 03/28] arm64/sysreg: Allow leading blanks on comments in sysreg file Mark Brown
2022-07-04 17:02 ` [PATCH v7 04/28] arm64/sysreg: Add SYS_FIELD_GET() helper Mark Brown
2022-07-04 17:02 ` [PATCH v7 05/28] arm64/cache: Restrict which headers are included in __ASSEMBLY__ Mark Brown
2022-07-04 17:02 ` [PATCH v7 06/28] arm64/sysreg: Standardise naming for CTR_EL0 fields Mark Brown
2022-07-04 17:02 ` [PATCH v7 07/28] arm64/sysreg: Standardise naming for DCZID_EL0 field names Mark Brown
2022-07-04 17:02 ` [PATCH v7 08/28] arm64/mte: Standardise GMID field name definitions Mark Brown
2022-07-04 17:02 ` [PATCH v7 09/28] arm64/sysreg: Align pointer auth enumeration defines with architecture Mark Brown
2022-07-04 17:02 ` [PATCH v7 10/28] arm64/sysreg: Make BHB clear feature defines match the architecture Mark Brown
2022-07-04 17:02 ` [PATCH v7 11/28] arm64/sysreg: Standardise naming for WFxT defines Mark Brown
2022-07-04 17:02 ` [PATCH v7 12/28] arm64/sysreg: Standardise naming for ID_AA64SMFR0_EL1 enums Mark Brown
2022-07-04 17:02 ` [PATCH v7 13/28] arm64/sysreg: Standardise naming for ID_AA64ZFR0_EL1 fields Mark Brown
2022-07-04 17:02 ` [PATCH v7 14/28] arm64/sysreg: Remove defines for RPRES enumeration Mark Brown
2022-07-04 17:02 ` [PATCH v7 15/28] arm64/sysreg: Add _EL1 into ID_AA64ISAR1_EL1 definition names Mark Brown
2022-07-04 17:02 ` [PATCH v7 16/28] arm64/sysreg: Add _EL1 into ID_AA64ISAR2_EL1 " Mark Brown
2022-07-04 17:02 ` [PATCH v7 17/28] arm64/sysreg: Convert CTR_EL0 to automatic generation Mark Brown
2022-07-04 17:02 ` [PATCH v7 18/28] arm64/sysreg: Convert DCZID_EL0 " Mark Brown
2022-07-04 17:02 ` [PATCH v7 19/28] arm64/sysreg: Convert GMID " Mark Brown
2022-07-04 17:02 ` [PATCH v7 20/28] arm64/sysreg: Convert ID_AA64ISAR1_EL1 " Mark Brown
2022-07-04 17:02 ` [PATCH v7 21/28] arm64/sysreg: Convert ID_AA64ISAR2_EL1 " Mark Brown
2022-07-04 17:02 ` [PATCH v7 22/28] arm64/sysreg: Convert LORSA_EL1 " Mark Brown
2022-07-04 17:02 ` [PATCH v7 23/28] arm64/sysreg: Convert LOREA_EL1 " Mark Brown
2022-07-04 17:02 ` [PATCH v7 24/28] arm64/sysreg: Convert LORN_EL1 " Mark Brown
2022-07-04 17:02 ` [PATCH v7 25/28] arm64/sysreg: Convert LORC_EL1 " Mark Brown
2022-07-04 17:03 ` [PATCH v7 26/28] arm64/sysreg: Convert LORID_EL1 " Mark Brown
2022-07-04 17:03 ` [PATCH v7 27/28] arm64/sysreg: Convert ID_AA64SMFR0_EL1 " Mark Brown
2022-07-04 17:03 ` Mark Brown [this message]
2022-07-05 13:31 ` [PATCH v7 00/28] arm64/sysreg: More system register generation Will Deacon

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