From: "Pali Rohár" <pali@kernel.org>
To: Jim Quinlan <jim2101024@gmail.com>
Cc: linux-pci@vger.kernel.org,
"Nicolas Saenz Julienne" <nsaenz@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Cyril Brulebois" <kibi@debian.org>,
bcm-kernel-feedback-list@broadcom.com,
james.quinlan@broadcom.com,
"Florian Fainelli" <f.fainelli@gmail.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-rpi-kernel@lists.infradead.org>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>,
"open list" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 2/6] PCI: brcmstb: Split brcm_pcie_setup() into two funcs
Date: Mon, 18 Jul 2022 15:11:31 +0200 [thread overview]
Message-ID: <20220718131131.dclndpkkh7yojhj4@pali> (raw)
In-Reply-To: <20220716222454.29914-3-jim2101024@gmail.com>
Hello!
On Saturday 16 July 2022 18:24:49 Jim Quinlan wrote:
> @@ -948,6 +941,40 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> if (pcie->gen)
> brcm_pcie_set_gen(pcie, pcie->gen);
>
> + /* Don't advertise L0s capability if 'aspm-no-l0s' */
> + aspm_support = PCIE_LINK_STATE_L1;
> + if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
> + aspm_support |= PCIE_LINK_STATE_L0S;
> + tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
> + u32p_replace_bits(&tmp, aspm_support,
> + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
> + writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
> +
> + /*
> + * For config space accesses on the RC, show the right class for
> + * a PCIe-PCIe bridge (the default setting is to be EP mode).
> + */
> + tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3);
> + u32p_replace_bits(&tmp, 0x060400,
There is already macro PCI_CLASS_BRIDGE_PCI_NORMAL, so please use it
instead of magic constant.
I introduced it recently in commit:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=904b10fb189cc15376e9bfce1ef0282e68b0b004
> + PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK);
> + writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3);
> +
> + return 0;
> +}
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next prev parent reply other threads:[~2022-07-18 13:12 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-16 22:24 [PATCH v2 0/6] PCI: brcmstb: Re-submit reverted patchset Jim Quinlan
2022-07-16 22:24 ` [PATCH v2 1/6] PCI: brcmstb: Remove unnecessary forward declarations Jim Quinlan
2022-07-16 22:24 ` [PATCH v2 2/6] PCI: brcmstb: Split brcm_pcie_setup() into two funcs Jim Quinlan
2022-07-18 13:11 ` Pali Rohár [this message]
2022-07-18 13:37 ` Jim Quinlan
2022-07-18 17:05 ` Bjorn Helgaas
2022-07-18 18:01 ` Pali Rohár
2022-07-18 18:14 ` Bjorn Helgaas
2022-07-18 18:56 ` Jim Quinlan
2022-07-18 19:23 ` Bjorn Helgaas
2022-07-18 22:40 ` Bjorn Helgaas
2022-07-19 13:08 ` Jim Quinlan
2022-07-19 20:03 ` Bjorn Helgaas
2022-07-20 14:53 ` Jim Quinlan
2022-07-20 16:18 ` Rob Herring
2022-07-20 21:34 ` Florian Fainelli
2022-07-21 14:27 ` Rob Herring
2022-07-18 22:40 ` Bjorn Helgaas
2022-07-20 20:37 ` Bjorn Helgaas
2022-07-21 14:56 ` Jim Quinlan
2022-07-21 16:10 ` Bjorn Helgaas
2022-07-16 22:24 ` [PATCH v2 3/6] PCI: brcmstb: Add "refusal mode" to preclude PCIe-induced CPU aborts Jim Quinlan
2022-07-20 22:05 ` Bjorn Helgaas
2022-07-21 14:53 ` Jim Quinlan
2022-07-21 15:46 ` Bjorn Helgaas
2022-07-20 22:08 ` Bjorn Helgaas
2022-07-16 22:24 ` [PATCH v2 4/6] PCI: brcmstb: Add mechanism to turn on subdev regulators Jim Quinlan
2022-07-16 22:24 ` [PATCH v2 5/6] PCI: brcmstb: Add control of subdevice voltage regulators Jim Quinlan
2022-07-16 22:24 ` [PATCH v2 6/6] PCI: brcmstb: Do not turn off WOL regulators on suspend Jim Quinlan
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