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Wed, 10 Aug 2022 21:13:42 +0000 Received: from offworld (unknown [104.36.25.245]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dave@stgolabs.net) by pdx1-sub0-mail-a301.dreamhost.com (Postfix) with ESMTPSA id 4M32jc5wMYz64; Wed, 10 Aug 2022 14:13:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=stgolabs.net; s=dreamhost; t=1660166021; bh=e1bm2IP5sdf1tCIrl5T23ze6bEl+DGHSYHzaFyz8rEo=; h=Date:From:To:Cc:Subject:Content-Type; b=A5K6iDwodcK6bM0P/mUDtKfab9ELJl8ZVSQTJL+iIC3xLsFelM8BWgnN5h+6H1Y4a t7g9m/gyPNKmQSVCK4T4z9ZRGHmLBZ2zgtqAnf10PSx5zn+RtjFd+pvg531NntEw4c ETUuYhZq9hTgXm38+M7sYoxCzrN+VlabHw5CcH4SRpmdrDPlwAXqBuhPG37F2huBuw 2jh/gLiHpi4TKlVwXa3PcDLKUDTini8LpGCAcaBlgQ7sfm8nz7Hc34W84oHbhQbAFi ZIEWWdIqgSM66YTAmxOJ453R/roNMnPbN91X1teB4Embw7HtRH/Y4EPn5hW02jJOzx lPwEyZ7kmMleQ== Date: Wed, 10 Aug 2022 14:13:37 -0700 From: Davidlohr Bueso To: Dan Williams Cc: Mark Rutland , Dave Jiang , Jonathan Cameron , linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev, bwidawsk@kernel.org, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, a.manzanares@samsung.com, linux-arch@vger.kernel.org, Arnd Bergmann , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH RFC 10/15] x86: add an arch helper function to invalidate all cache for nvdimm Message-ID: <20220810211337.ha27cl24splm4wjh@offworld> References: <165791918718.2491387.4203738301057301285.stgit@djiang5-desk3.ch.intel.com> <165791937063.2491387.15277418618265930924.stgit@djiang5-desk3.ch.intel.com> <20220718053039.5whjdcxynukildlo@offworld> <4bedc81d-62fa-7091-029e-a2e56b4f8f7a@intel.com> <20220803183729.00002183@huawei.com> <9f3705e1-de21-0f3c-12af-fd011b6d613d@intel.com> <62f40fba338af_3ce6829466@dwillia2-xfh.jf.intel.com.notmuch> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <62f40fba338af_3ce6829466@dwillia2-xfh.jf.intel.com.notmuch> User-Agent: NeoMutt/20220429 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220810_141349_383880_49D76775 X-CRM114-Status: GOOD ( 13.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 10 Aug 2022, Dan Williams wrote: >I expect the interface would not be in the "flush_cache_" namespace >since those functions are explicitly for virtually tagged caches that >need maintenance on TLB operations that change the VA to PA association. >In this case the cache needs maintenance because the data at the PA >changes. That also means that putting it in the "nvdimm_" namespace is >also wrong because there are provisions in the CXL spec where volatile >memory ranges can also change contents at a given PA, for example caches >might need to be invalidated if software resets the device, but not the >platform. > >Something like: > > region_cache_flush(resource_size_t base, resource_size_t n, bool nowait) > >...where internally that function can decide if it can rely on an >instruction like wbinvd, use set / way based flushing (if set / way >maintenance can be made to work which sounds like no for arm64), or map >into VA space and loop. If it needs to fall back to that VA-based loop >it might be the case that the caller would want to just fail the >security op rather than suffer the loop latency. Yep, I was actually prototyping something similar, but want to still reuse cacheflush.h machinery and just introduce cache_flush_region() or whatever name, which returns any error. So all the logic would just be per-arch, where x86 will do the wbinv and return 0, and arm64 can just do -EINVAL until VA-based is no longer the only way. Thanks, Davidlohr _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel