From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E19A1C25B06 for ; Sun, 14 Aug 2022 20:43:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=iB6x70QxQM/rOUhs2YywW5fp/uh6L8PMzM9ZpO/z/3g=; b=GgzPhfiIVwx/T1 evfCIGjXxzbhrtkfIL8VY2M/oIoGjgZD9Pv5ZhxycW077DLsMlV8aJh5wPmPlZ9OyA0PRH7DMHChq aH/oaCBUZgbW4JudArNsiPrFRLpobAgkDDzyFHL7s8+7YlPXzW/PBusQXNEjfK0TW8AWO8nctP4vv cEdR7PjARLo6UxSzFU/HsDAmlz7v1vuS4WINEhbS3egynFWJ8KXNVXELywZYAYE8vJInC5UffR/fg 2xN82CSAtfpVSBvqF/OwgSP2Fct7IwKkvf8ZrCakTNeirFrRkdw05dXxNll6bkfsFC+at0Z5lZgHg nO+Z0OGROV9LCnf4lATQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oNKQf-00949O-NY; Sun, 14 Aug 2022 20:41:50 +0000 Received: from mail-oi1-f178.google.com ([209.85.167.178]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oNKQc-009489-Ia for linux-arm-kernel@lists.infradead.org; Sun, 14 Aug 2022 20:41:48 +0000 Received: by mail-oi1-f178.google.com with SMTP id l188so6867937oia.4 for ; Sun, 14 Aug 2022 13:41:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc; bh=9Mv3SYsV787hG2zwBPi7bzT81bYQL5Y4bZ2g9jjPhSI=; b=fxzmlk6SHe7jasnNetSgLd1YmlhUCleY0hCWEwveNWZ9weDcD2q/2jylh9B8ZMRWHF kiEgmhjImXB3LbYUl7XBLdZ62Fa/VjnuNZMF/OHwpnGo5pi23nUIg2QEAQQPX56R8gVP 9xt7i6uptnXo7/0YmmstEnVuJu0xowsIHBNcH5xOO28fkZKarhNQsogpibugOtxu4xvz +4aa+yKXcU3bCUBzuwyUCW5w44Z5bg9GYSzeoiwv+nzr8M/tZdPIV6GI2HaDt4c2tZyv ZHS3lSHtwd8m65Sxtd4JZ8R2gbDOLO4I+6JQ/HXEsT/eM85joP197h4YlBQW7/6BUiJK FkSg== X-Gm-Message-State: ACgBeo1d47X/ozcMnUizc14LT1m4CHSmWmw82Rh1fxOTWV8DdGnzy4QG ay3bN+NPYLN38aqpoi3OpQ== X-Google-Smtp-Source: AA6agR4uHGL9LB7gP7Q+Ajfe9FgPloWZ0Sz4kuzRLczXQqy+Qp+hbqAqrIq7K9g49rj7+MI+CQqFBQ== X-Received: by 2002:a05:6808:10ce:b0:342:a33c:fcc with SMTP id s14-20020a05680810ce00b00342a33c0fccmr5836922ois.250.1660509702872; Sun, 14 Aug 2022 13:41:42 -0700 (PDT) Received: from robh.at.kernel.org ([172.58.176.57]) by smtp.gmail.com with ESMTPSA id r14-20020a05687032ce00b0011b98fa9ab5sm396327oac.50.2022.08.14.13.41.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Aug 2022 13:41:42 -0700 (PDT) Received: (nullmailer pid 672588 invoked by uid 1000); Sun, 14 Aug 2022 20:41:38 -0000 Date: Sun, 14 Aug 2022 14:41:38 -0600 From: Rob Herring To: Frank Li Cc: maz@kernel.org, tglx@linutronix.de, krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kw@linux.com, bhelgaas@google.com, kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, peng.fan@nxp.com, aisheng.dong@nxp.com, jdmason@kudzu.us, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, kishon@ti.com, lorenzo.pieralisi@arm.com, ntb@lists.linux.dev, lznuaa@gmail.com Subject: Re: [PATCH v4 3/4] dt-bindings: irqchip: imx mu work as msi controller Message-ID: <20220814204138.GA664328-robh@kernel.org> References: <20220812215242.2255824-1-Frank.Li@nxp.com> <20220812215242.2255824-4-Frank.Li@nxp.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220812215242.2255824-4-Frank.Li@nxp.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220814_134146_637862_AC0DAB4C X-CRM114-Status: GOOD ( 21.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Aug 12, 2022 at 04:52:41PM -0500, Frank Li wrote: > I.MX mu support generate irq by write a register. Provide msi controller > support so other driver such as PCI EP can use it by standard msi > interface as doorbell. > > Signed-off-by: Frank Li > --- > .../interrupt-controller/fsl,mu-msi.yaml | 93 +++++++++++++++++++ > 1 file changed, 93 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml > new file mode 100644 > index 0000000000000..f60fa8b686879 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml > @@ -0,0 +1,93 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NXP i.MX Messaging Unit (MU) work as msi controller > + > +maintainers: > + - Frank Li > + > +description: | > + The Messaging Unit module enables two processors within the SoC to > + communicate and coordinate by passing messages (e.g. data, status > + and control) through the MU interface. The MU also provides the ability > + for one processor (A side) to signal the other processor (B side) using > + interrupts. > + > + Because the MU manages the messaging between processors, the MU uses > + different clocks (from each side of the different peripheral buses). > + Therefore, the MU must synchronize the accesses from one side to the > + other. The MU accomplishes synchronization using two sets of matching > + registers (Processor A-facing, Processor B-facing). > + > + MU can work as msi interrupt controller to do doorbell > + > +allOf: > + - $ref: /schemas/interrupt-controller/msi-controller.yaml# > + > +properties: > + compatible: > + enum: > + - fsl,imx6sx-mu-msi > + - fsl,imx7ulp-mu-msi > + - fsl,imx8ulp-mu-msi > + - fsl,imx8ulp-mu-msi-s4 > + > + reg: > + items: > + - description: a side register base address > + - description: b side register base address > + > + reg-names: > + items: > + - const: a > + - const: b > + > + interrupts: > + description: a side interrupt number. How many? > + > + clocks: > + maxItems: 1 > + > + power-domains: > + items: > + - description: a side power domain > + - description: b side power domain > + > + power-domain-names: > + items: > + - const: a > + - const: b > + > + interrupt-controller: true > + > + msi-controller: true #msi-cells? (Missing is treated as 0, but new bindings should be explicit) > + > +required: > + - compatible > + - reg > + - interrupts > + - interrupt-controller > + - msi-controller > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + > + lsio_mu12: msi-controller@5d270000 { Drop unused labels. > + compatible = "fsl,imx6sx-mu-msi"; > + msi-controller; > + interrupt-controller; > + reg = <0x5d270000 0x10000>, /* A side */ > + <0x5d300000 0x10000>; /* B side */ > + reg-names = "a", "b"; > + interrupts = ; > + power-domains = <&pd IMX_SC_R_MU_12A>, > + <&pd IMX_SC_R_MU_12B>; > + power-domain-names = "a", "b"; > + }; > -- > 2.35.1 > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel