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Tue, 16 Aug 2022 18:10:41 +0000 Received: from offworld (unknown [104.36.25.245]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dave@stgolabs.net) by pdx1-sub0-mail-a314.dreamhost.com (Postfix) with ESMTPSA id 4M6fMg1vT2zF1; Tue, 16 Aug 2022 11:10:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=stgolabs.net; s=dreamhost; t=1660673440; bh=I06/ecHUnT7zHJJuTwo7ZmgJud65PxCU9WXUPwrIBaQ=; h=Date:From:To:Cc:Subject:Content-Type; b=VbXvJHvNVTgML/Vi2Xzn9FVbgGkc7dXYyKl1bUJv0Ja4nIaHHN3gzyVfyhk+zwJ5B TD/Q49GkQIumI6/TXj6i85nLbJipITDDOitrbVF5YvIDO7C+z1hhfdBLYW1ilhIZUO +HtNsN4hBOgoagNOtsGaDOp5pVqv66Y2g6wMILpTY04oC+R9Plh6JfdTPgiE/pgJSW 1Ly6s88hI95jSQ2gb/NMM9w5vqJCgFfk37lKd7meKs430vKwr50QrTnf8IgJCl4GZL mEl5SjC0Zcg7ZhW1FTbirTL+KPuc2CLssRW1LCk9qstOU5Zpan3DfkE8vrvl5llHXO k+s6laKDg1ZcQ== Date: Tue, 16 Aug 2022 10:52:59 -0700 From: Davidlohr Bueso To: Dan Williams Cc: Peter Zijlstra , Mark Rutland , Dave Jiang , Jonathan Cameron , linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev, bwidawsk@kernel.org, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, a.manzanares@samsung.com, linux-arch@vger.kernel.org, Arnd Bergmann , linux-arm-kernel@lists.infradead.org, bp@alien8.de, x86@kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arch/cacheflush: Introduce flush_all_caches() Message-ID: <20220816175259.o5h5wv23rs2bvcu6@offworld> References: <4bedc81d-62fa-7091-029e-a2e56b4f8f7a@intel.com> <20220803183729.00002183@huawei.com> <9f3705e1-de21-0f3c-12af-fd011b6d613d@intel.com> <62f40fba338af_3ce6829466@dwillia2-xfh.jf.intel.com.notmuch> <20220815160706.tqd42dv24tgb7x7y@offworld> <62fbcae511ec1_dfbc129453@dwillia2-xfh.jf.intel.com.notmuch> <20220816165301.4m4w6zsse62z4hxz@offworld> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20220429 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220816_111044_460279_34C80904 X-CRM114-Status: GOOD ( 17.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 16 Aug 2022, Dan Williams wrote: >On Tue, Aug 16, 2022 at 10:30 AM Davidlohr Bueso wrote: >> >> On Tue, 16 Aug 2022, Dan Williams wrote: >> >> >Peter Zijlstra wrote: >> >> On Mon, Aug 15, 2022 at 09:07:06AM -0700, Davidlohr Bueso wrote: >> >> > diff --git a/arch/x86/include/asm/cacheflush.h b/arch/x86/include/asm/cacheflush.h >> >> > index b192d917a6d0..ce2ec9556093 100644 >> >> > --- a/arch/x86/include/asm/cacheflush.h >> >> > +++ b/arch/x86/include/asm/cacheflush.h >> >> > @@ -10,4 +10,7 @@ >> >> > >> >> > void clflush_cache_range(void *addr, unsigned int size); >> >> > >> >> > +#define flush_all_caches() \ >> >> > + do { wbinvd_on_all_cpus(); } while(0) >> >> > + >> >> >> >> This is horrific... we've done our utmost best to remove all WBINVD >> >> usage and here you're adding it back in the most horrible form possible >> >> ?!? >> >> >> >> Please don't do this, do *NOT* use WBINVD. >> > >> >Unfortunately there are a few good options here, and the changelog did >> >not make clear that this is continuing legacy [1], not adding new wbinvd >> >usage. >> >> While I was hoping that it was obvious from the intel.c changes that this >> was not a new wbinvd, I can certainly improve the changelog with the below. > >I also think this cache_flush_region() API wants a prominent comment >clarifying the limited applicability of this API. I.e. that it is not >for general purpose usage, not for VMs, and only for select bare metal >scenarios that instantaneously invalidate wide swaths of memory. >Otherwise, I can now see how this looks like a potentially scary >expansion of the usage of wbinvd. Sure. Also, in the future we might be able to bypass this hammer in the presence of persistent cpu caches. Thanks, Davidlohr _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel