From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 617CDC25B08 for ; Wed, 17 Aug 2022 21:50:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=vyVf/cYusmSJrMlgn3IwZA+4HLNRwdV56bTuvNxpr7M=; b=y1M+otpPjLcDgl wTvOtblpoSgQSSuUoXZO/m3dgWa7evGrZEZYT4nmP/EOOkUpqPFP1NGNNbgzxswLjYioUhAPM1Y0q qCHRFMLB+ulcUzHyqvAEbApnkAI/Z8fRGK/fXnu4h/t/GWU/UfXSRiVVyvgu/XpWzqT5lkrJz2jMW WHS16FMXZMEryqZA77dXpL5bW272ElcE+/PvRsifMW6xfJayjxhJs2EAGv+M6tYzVZyU16MCt235G 1uco9X2zSX4n/hRsnYMnnL4+P1K4L4GuvBqECCdABqTqOKliqR7v+8evTDh4kpqksPbDiLivHXFKU YZK9VfBovtAmwc5Okxxg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOQuq-007Cct-3a; Wed, 17 Aug 2022 21:49:32 +0000 Received: from out2.migadu.com ([2001:41d0:2:aacc::]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOQu5-007C8Q-Lu for linux-arm-kernel@lists.infradead.org; Wed, 17 Aug 2022 21:48:50 +0000 X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1660772917; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=cDVlBOelWFV15LvLWa+pCIh5Az2QchuTMm2O7H0MfZk=; b=puD8I3PkQRNayksEy0wOfU5b0YzxoKZaMjrXlFl+3KOT9ZugR1UJ41zWBQ4rIUp7WgJmYP zer8g0/Qivf8EkqpyOrgj/kSI9u4kcW+RqBS5h0Sw26FxOJKXuml5SvL9BIxtorjjBp7Ck 3/FsLgpUpC7mZFkmblRFxfhBznj563c= From: Oliver Upton To: kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, maz@kernel.org, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com, will@kernel.org, Oliver Upton Subject: [PATCH 0/6] KVM: arm64: Treat 32bit ID registers as RAZ/WI on 64bit-only system Date: Wed, 17 Aug 2022 21:48:12 +0000 Message-Id: <20220817214818.3243383-1-oliver.upton@linux.dev> MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT X-Migadu-Auth-User: linux.dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220817_144846_870426_728BE448 X-CRM114-Status: UNSURE ( 8.48 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org For reasons unknown, the Arm architecture defines the 64-bit views of the 32-bit ID registers as UNKNOWN [1]. This combines poorly with the fact that KVM unconditionally exposes these registers to userspace, which could throw a wrench in migration between 64-bit only systems. This series reworks KVM's definition of these registers to RAZ/WI with the goal of providing consistent register values across 64-bit machines. Patches 1-2 clean up some of the ID register accessors, taking advantage of the fact that the generic ones already know how to handle RAZ registers. Patches 3-4 wire in a new visibility bit to indicate a register ignores writes from userspace. Patch 5 moves all exposed 32-bit ID registers to have RAZ/WI behavior on 64-bit only systems. Note that hidden 32-bit registers continue to have RAZ behavior and carry the additional requirement of invariance. Lastly, patch 6 tests that userspace and guest indeed see the registers as RAZ/WI. Applies to 6.0-rc1 + the mismatched system fixes [2] picked up earlier today. Tested on the fast model, both with mismatched AArch32 support and no AArch32 support whatoever. [1]: DDI0487H.a Table D12-2 'Instruction encodings for non-Debug System Register accesses' [2]: https://lore.kernel.org/kvmarm/20220816192554.1455559-1-oliver.upton@linux.dev/ Oliver Upton (6): KVM: arm64: Use visibility hook to treat ID regs as RAZ KVM: arm64: Remove internal accessor helpers for id regs KVM: arm64: Spin off helper for calling visibility hook KVM: arm64: Add a visibility bit to ignore user writes KVM: arm64: Treat 32bit ID registers as RAZ/WI on 64bit-only system KVM: selftests: Add test for RAZ/WI AArch32 ID registers arch/arm64/kvm/sys_regs.c | 137 +++++++++--------- arch/arm64/kvm/sys_regs.h | 24 ++- tools/testing/selftests/kvm/.gitignore | 1 + tools/testing/selftests/kvm/Makefile | 1 + .../kvm/aarch64/aarch64_only_id_regs.c | 135 +++++++++++++++++ 5 files changed, 222 insertions(+), 76 deletions(-) create mode 100644 tools/testing/selftests/kvm/aarch64/aarch64_only_id_regs.c -- 2.37.1.595.g718a3a8f04-goog _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel