From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CD6C6C00140 for ; Thu, 18 Aug 2022 12:34:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=EQZY9uaaGrAuu5bUXZAJ6l54TLbaQR5wb6rLqV4BvY0=; b=bnImrISPxzfts2 48Z8pg+zgWanTY5CfD8/l3yFc+NS2DVj/t1g6uDCPaesuNgb77pekrLG0XmyjXeQEqSfEzjD5Pg87 Ow5CuXHH3NQdvEBOXSYHXxZtjtoPqfOJwcba/KOeRk2UlUSRVEwXWOQvrNeRNdfDuxwhWrcToml27 VTzs6Lniqi1EetAUpVYpq2XL0bz9gA26e5BrjbRrQiH6VqoNZuiBGj1U/7cWBsS16ABH1u29B25an mJw+RXj7WU4PQw5K2DvttRV2acxAfHJPePT1lmFGo1JM/iZTRHK5i4vFQwOVSFWGjIiQcPMbHrLw9 tvB0zXEs0QcWmRMhXIgQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOehb-004d7j-0X; Thu, 18 Aug 2022 12:32:47 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOedV-004ZhG-Th for linux-arm-kernel@lists.infradead.org; Thu, 18 Aug 2022 12:28:39 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 79F0861592; Thu, 18 Aug 2022 12:28:33 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 76370C433D6; Thu, 18 Aug 2022 12:28:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1660825712; bh=L/+HRkc9YplYeJhyr6lrv+HbIboLvVzcrUrE7iX2FxY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HyS+yMvcio/GkZUCryyEN7D4zB33kduJvPCJl7Yy6CkOn6Pz51RvU7gL/fUZc9XDK /BV6vaOBq+0Gf98Az44M2EFWdsauSK7m8U4arcWGahri5/7TLCK7lfzRR0U+4AoBoU 0yzJmk2+j/h0OU7veIoabevLJDWF1M/j55UHQrmiTxGY1fV/oI56o5roof6S3YCbxv odu4rq/G3aLo3HvceoPJ5O/n5rngbJnIFwYayaol/7EWlfCckUfmOp14dpJkK1NF9t 5SxP+oS5nSRMkcAg3ZK30YoVKtFLYUn3LmzB4+X+zdRRUOPKre3KGoPwJl4j6gEAVs 2vevbV6ypDVig== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Kristina Martsenko , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v4 09/28] arm64/sysreg: Standardise naming of ID_AA64MMFR0_EL1.ASIDBits Date: Thu, 18 Aug 2022 13:24:06 +0100 Message-Id: <20220818122425.37889-10-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220818122425.37889-1-broonie@kernel.org> References: <20220818122425.37889-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4388; i=broonie@kernel.org; h=from:subject; bh=L/+HRkc9YplYeJhyr6lrv+HbIboLvVzcrUrE7iX2FxY=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBi/i9m3KdTzijL/DTtNz1l7XYZ6HcVlntOkhHAoZq1 Tsi4D9uJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYv4vZgAKCRAk1otyXVSH0NSrB/ 9GSmW6x85KpEnoZyGiWQnQdNAvHdo1WlsAfMxKKt7+abcnc7EY8/uaClY+58IYiD8AjhqVIwIh0ure BcRh+KW30fgpfPsxYfFriJk5hJRAUd2BLsAaxQggdCzDCeMQmkNYlHnINq8E6mRC5W0cOb+06ZqgCQ 5+t5DH2Dp63LN2+949U+AKFtZdjFbmmV6svP7L5cxOQV82Y7Ve0YkzI3IAGG39Kvrkm2foALiE9bfC S3vtUL5aB/AxD7clyFZgAXYje6vl1eWx4hAiyyIx9pZ8m2y6mxZTFnST3HDZFa0LpsZat6JKQ9B2D1 Z/CETJPQT39FbMKo84RSKpCHpdvoTo X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220818_052834_095941_9274223F X-CRM114-Status: GOOD ( 16.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org For some reason we refer to ID_AA64MMFR0_EL1.ASIDBits as ASID. Add BITS into the name, bringing the naming into sync with DDI0487H.a. Due to the large amount of MixedCase in this register which isn't really consistent with either the kernel style or the majority of the architecture the use of upper case is preserved. No functional changes. Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 6 +++--- arch/arm64/kernel/cpufeature.c | 2 +- arch/arm64/kvm/hyp/include/nvhe/fixed_config.h | 2 +- arch/arm64/mm/context.c | 6 +++--- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 2 +- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index cc70d0ebffa2..842b0cb8c4e2 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -745,11 +745,11 @@ #define ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT 16 #define ID_AA64MMFR0_EL1_SNSMEM_SHIFT 12 #define ID_AA64MMFR0_EL1_BIGEND_SHIFT 8 -#define ID_AA64MMFR0_EL1_ASID_SHIFT 4 +#define ID_AA64MMFR0_EL1_ASIDBITS_SHIFT 4 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT 0 -#define ID_AA64MMFR0_EL1_ASID_8 0x0 -#define ID_AA64MMFR0_EL1_ASID_16 0x2 +#define ID_AA64MMFR0_EL1_ASIDBITS_8 0x0 +#define ID_AA64MMFR0_EL1_ASIDBITS_16 0x2 #define ID_AA64MMFR0_EL1_TGRAN4_NI 0xf #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 0x0 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 4c0bc39d1dc3..0d0b599fbfd5 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -352,7 +352,7 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { /* Linux shouldn't care about secure memory */ ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASID_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), /* * Differing PARange is fine as long as all peripherals and memory are mapped * within the minimum PARange of all CPUs diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h index 0ece26707fc0..0c2e474d0c9e 100644 --- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h +++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h @@ -87,7 +87,7 @@ */ #define PVM_ID_AA64MMFR0_RESTRICT_UNSIGNED (\ FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_PARANGE), ID_AA64MMFR0_EL1_PARANGE_40) | \ - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_ASID), ID_AA64MMFR0_EL1_ASID_16) \ + FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_ASIDBITS), ID_AA64MMFR0_EL1_ASIDBITS_16) \ ) /* diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index 8f38a5452d05..e1e0dca01839 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -43,17 +43,17 @@ static u32 get_cpu_asid_bits(void) { u32 asid; int fld = cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64MMFR0_EL1), - ID_AA64MMFR0_EL1_ASID_SHIFT); + ID_AA64MMFR0_EL1_ASIDBITS_SHIFT); switch (fld) { default: pr_warn("CPU%d: Unknown ASID size (%d); assuming 8-bit\n", smp_processor_id(), fld); fallthrough; - case ID_AA64MMFR0_EL1_ASID_8: + case ID_AA64MMFR0_EL1_ASIDBITS_8: asid = 8; break; - case ID_AA64MMFR0_EL1_ASID_16: + case ID_AA64MMFR0_EL1_ASIDBITS_16: asid = 16; } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c index da67a75cdaad..5968a568aae2 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -431,7 +431,7 @@ bool arm_smmu_sva_supported(struct arm_smmu_device *smmu) return false; /* We can support bigger ASIDs than the CPU, but not smaller */ - fld = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_EL1_ASID_SHIFT); + fld = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT); asid_bits = fld ? 16 : 8; if (smmu->asid_bits < asid_bits) return false; -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel