From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
Kristina Martsenko <kristina.martsenko@arm.com>,
linux-arm-kernel@lists.infradead.org,
Mark Brown <broonie@kernel.org>
Subject: [PATCH v4 16/28] arm64/sysreg: Standardise naming for MTE feature enumeration
Date: Thu, 18 Aug 2022 13:24:13 +0100 [thread overview]
Message-ID: <20220818122425.37889-17-broonie@kernel.org> (raw)
In-Reply-To: <20220818122425.37889-1-broonie@kernel.org>
In preparation for conversion to automatic generation refresh the names
given to the items in the MTE feture enumeration to reflect our standard
pattern for naming, corresponding to the architecture feature names they
reflect. No functional change.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/cpufeature.h | 2 +-
arch/arm64/include/asm/sysreg.h | 6 +++---
arch/arm64/kernel/cpufeature.c | 8 ++++----
arch/arm64/mm/proc.S | 2 +-
4 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index 5fc43f7f3ed6..79bb9e58d9c6 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -633,7 +633,7 @@ static inline bool id_aa64pfr1_mte(u64 pfr1)
{
u32 val = cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_EL1_MTE_SHIFT);
- return val >= ID_AA64PFR1_EL1_MTE;
+ return val >= ID_AA64PFR1_EL1_MTE_MTE2;
}
void __init setup_cpu_features(void);
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 7beafc57df94..05a90fe48025 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -727,9 +727,9 @@
#define ID_AA64PFR1_EL1_SME 1
#define ID_AA64PFR1_EL1_MTE_NI 0x0
-#define ID_AA64PFR1_EL1_MTE_EL0 0x1
-#define ID_AA64PFR1_EL1_MTE 0x2
-#define ID_AA64PFR1_EL1_MTE_ASYMM 0x3
+#define ID_AA64PFR1_EL1_MTE_IMP 0x1
+#define ID_AA64PFR1_EL1_MTE_MTE2 0x2
+#define ID_AA64PFR1_EL1_MTE_MTE3 0x3
/* id_aa64mmfr0 */
#define ID_AA64MMFR0_EL1_ECV_SHIFT 60
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index b887b79f3978..e08d10dc2444 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2540,7 +2540,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.sys_reg = SYS_ID_AA64PFR1_EL1,
.field_pos = ID_AA64PFR1_EL1_MTE_SHIFT,
.field_width = 4,
- .min_field_value = ID_AA64PFR1_EL1_MTE,
+ .min_field_value = ID_AA64PFR1_EL1_MTE_MTE2,
.sign = FTR_UNSIGNED,
.cpu_enable = cpu_enable_mte,
},
@@ -2552,7 +2552,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.sys_reg = SYS_ID_AA64PFR1_EL1,
.field_pos = ID_AA64PFR1_EL1_MTE_SHIFT,
.field_width = 4,
- .min_field_value = ID_AA64PFR1_EL1_MTE_ASYMM,
+ .min_field_value = ID_AA64PFR1_EL1_MTE_MTE3,
.sign = FTR_UNSIGNED,
},
#endif /* CONFIG_ARM64_MTE */
@@ -2745,8 +2745,8 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
#endif
#ifdef CONFIG_ARM64_MTE
- HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE),
- HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_MTE_ASYMM, CAP_HWCAP, KERNEL_HWCAP_MTE3),
+ HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_MTE_MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE),
+ HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_MTE_MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3),
#endif /* CONFIG_ARM64_MTE */
HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 15539da36bc3..5f7784ee6044 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -435,7 +435,7 @@ SYM_FUNC_START(__cpu_setup)
*/
mrs x10, ID_AA64PFR1_EL1
ubfx x10, x10, #ID_AA64PFR1_EL1_MTE_SHIFT, #4
- cmp x10, #ID_AA64PFR1_EL1_MTE
+ cmp x10, #ID_AA64PFR1_EL1_MTE_MTE2
b.lt 1f
/* Normal Tagged memory type at the corresponding MAIR index */
--
2.30.2
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next prev parent reply other threads:[~2022-08-18 12:41 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-18 12:23 [PATCH v4 00/28] arm64/sysreg: More system register generation Mark Brown
2022-08-18 12:23 ` [PATCH v4 01/28] arm64/sysreg: Remove stray SMIDR_EL1 defines Mark Brown
2022-08-18 12:23 ` [PATCH v4 02/28] arm64/sysreg: Describe ID_AA64SMFR0_EL1.SMEVer as an enumeration Mark Brown
2022-08-18 12:24 ` [PATCH v4 03/28] arm64: cache: Remove unused CTR_CACHE_MINLINE_MASK Mark Brown
2022-08-18 12:24 ` [PATCH v4 04/28] arm64/sysreg: Add _EL1 into ID_AA64MMFR0_EL1 definition names Mark Brown
2022-08-18 12:24 ` [PATCH v4 05/28] arm64/sysreg: Add _EL1 into ID_AA64MMFR2_EL1 " Mark Brown
2022-08-18 12:24 ` [PATCH v4 06/28] arm64/sysreg: Add _EL1 into ID_AA64PFR0_EL1 " Mark Brown
2022-08-18 12:24 ` [PATCH v4 07/28] arm64/sysreg: Add _EL1 into ID_AA64PFR1_EL1 constant names Mark Brown
2022-08-18 12:24 ` [PATCH v4 08/28] arm64/sysreg: Standardise naming of ID_AA64MMFR0_EL1.BigEnd Mark Brown
2022-08-18 12:24 ` [PATCH v4 09/28] arm64/sysreg: Standardise naming of ID_AA64MMFR0_EL1.ASIDBits Mark Brown
2022-08-18 12:24 ` [PATCH v4 10/28] arm64/sysreg: Standardise naming for ID_AA64MMFR1_EL1 fields Mark Brown
2022-08-18 12:24 ` [PATCH v4 11/28] arm64/sysreg: Standardise naming for ID_AA64MMFR2_EL1.VARange Mark Brown
2022-08-18 12:24 ` [PATCH v4 12/28] arm64/sysreg: Standardise naming for ID_AA64MMFR2_EL1.CnP Mark Brown
2022-08-18 12:24 ` [PATCH v4 13/28] arm64/sysreg: Standardise naming for ID_AA64PFR0_EL1 constants Mark Brown
2022-08-18 12:24 ` [PATCH v4 14/28] arm64/sysreg: Standardise naming for ID_AA64PFR0_EL1.AdvSIMD constants Mark Brown
2022-08-18 12:24 ` [PATCH v4 15/28] arm64/sysreg: Standardise naming for SSBS feature enumeration Mark Brown
2022-08-18 12:24 ` Mark Brown [this message]
2022-08-18 12:24 ` [PATCH v4 17/28] arm64/sysreg: Standardise naming of ID_AA64PFR1_EL1 fractional version fields Mark Brown
2022-08-18 12:24 ` [PATCH v4 18/28] arm64/sysreg: Standardise naming of ID_AA64PFR1_EL1 BTI enumeration Mark Brown
2022-08-18 12:24 ` [PATCH v4 19/28] arm64/sysreg: Standardise naming of ID_AA64PFR1_EL1 SME enumeration Mark Brown
2022-08-18 12:24 ` [PATCH v4 20/28] arm64/sysreg: Convert HCRX_EL2 to automatic generation Mark Brown
2022-08-18 12:24 ` [PATCH v4 21/28] arm64/sysreg: Convert ID_AA64MMFR0_EL1 " Mark Brown
2022-08-18 12:24 ` [PATCH v4 22/28] arm64/sysreg: Convert ID_AA64MMFR1_EL1 " Mark Brown
2022-08-18 12:24 ` [PATCH v4 23/28] arm64/sysreg: Convert ID_AA64MMFR2_EL1 " Mark Brown
2022-08-18 12:24 ` [PATCH v4 24/28] arm64/sysreg: Convert ID_AA64PFR0_EL1 " Mark Brown
2022-08-18 12:24 ` [PATCH v4 25/28] arm64/sysreg: Convert ID_AA64PFR1_EL1 " Mark Brown
2022-08-18 12:24 ` [PATCH v4 26/28] arm64/sysreg: Convert TIPDR_EL1 " Mark Brown
2022-08-18 12:24 ` [PATCH v4 27/28] arm64/sysreg: Convert SCXTNUM_EL1 " Mark Brown
2022-08-18 12:24 ` [PATCH v4 28/28] arm64/sysreg: Add defintion for ALLINT Mark Brown
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