From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 93834C32772 for ; Thu, 18 Aug 2022 20:08:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DkgJ449PmwrXooENdFsOWmJig7+0AUto0E3DVdWc/yc=; b=aBJQn0DIWE0bEc /0OYK+SSbYBvEI03ebAekpCBUg0cylwUQT4xS11l/esqAwnlQf6/I/S7tDCczSRDlg6I/4BIUNnwX C4CZSECizJwxjSvGSZPSRrR3QGakDtUhfl4EMCLoBWsO7UXPrujPnrlm1eWEN+7KasbYCIQBL0DAE LsH+Peq1lPnj3+Bxa1yxqBM45aZ3Wu5+db9T8bop4ZafkjZ4mqSFmcMy4tY9lDJSErN6nzC6riB8l X4KzRjE1RduUBnMwH9+xUHt4yBKpZe0VcPeYvH7Lw3ZYdJY7otZkJYfWeTrsnbBt/zs4VxIPsduaz F6R5SuKbQ6l+xmjel+Pw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOlnw-008zKF-KE; Thu, 18 Aug 2022 20:07:48 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOlns-008zI4-FL for linux-arm-kernel@lists.infradead.org; Thu, 18 Aug 2022 20:07:46 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 12EF2B82454; Thu, 18 Aug 2022 20:07:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6A2B0C433D6; Thu, 18 Aug 2022 20:07:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1660853260; bh=HqRuYKPKoRqwJbJeLclSyLBrd/IVtnMuG7MQd/VevCw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=jPsTfP/aPrMrzYy/HpSpqIzUeZYAjyghO9GBUtSIE7C0oEeVCPg3kyjMeYnLmDehn y/y7rqgCzbcVi8piPG/I3bhmbJtVTps5aj4CHhf9VBd2LiZiK0dByHsk7rA0IktQM+ ZzFoncm1N2UJKVPqlQv/+ZYSzYxpj3qmNAuJwCimQmUQqp8ZRUQYZTV5M03xRX7/vD Ael/mvXjJ+lwloqa1+vlKsYH+xDmqp46EulFfORNGBxQSFF9FsKPf0gqZfG8vrf5re 17kx56JqBYn0XOPTEjJNc1aZzev6m9zz4M/o0QfNUtNynHIbJF9hp5jf3GCZBZNfq9 lkWIlrUDb0hVQ== Received: by pali.im (Postfix) id 8AD44622; Thu, 18 Aug 2022 22:07:37 +0200 (CEST) Date: Thu, 18 Aug 2022 22:07:37 +0200 From: Pali =?utf-8?B?Um9ow6Fy?= To: Andrew Lunn Cc: Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Bjorn Helgaas , Rob Herring , Sebastian Hesselbarth , Gregory Clement , Thomas Petazzoni , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 2/4] PCI: mvebu: Implement support for interrupts on emulated bridge Message-ID: <20220818200737.7w2wqh62arfrskks@pali> References: <20220817230036.817-1-pali@kernel.org> <20220817230036.817-3-pali@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20180716 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220818_130744_836681_C01728C6 X-CRM114-Status: GOOD ( 25.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thursday 18 August 2022 21:51:21 Andrew Lunn wrote: > > -static irqreturn_t mvebu_pcie_irq_handler(int irq, void *arg) > > +static irqreturn_t mvebu_pcie_error_irq_handler(int irq, void *arg) > > +{ > > + struct mvebu_pcie_port *port = arg; > > + struct device *dev = &port->pcie->pdev->dev; > > + u32 cause, unmask, status; > > + > > + cause = mvebu_readl(port, PCIE_INT_CAUSE_OFF); > > + unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF); > > + status = cause & unmask; > > + > > + /* "error" interrupt handler does not process INTX interrupts */ > > + status &= ~(PCIE_INT_INTX(0) | PCIE_INT_INTX(1) | > > + PCIE_INT_INTX(2) | PCIE_INT_INTX(3)); > > Just for my understanding... > > There are two interrupts yes > but the status information what those > interrupts actually mean are all packed into one register? yes for masking individual interrupt events there is just one shared register for both "intx" and "error" interrupt source. and also there is also just one shared "cause" register which says which individual interrupt events happened. > I assume reading the clause register does not clear set bits? yes, reading does not clear any interrupt event. > Otherwise there > would be a race condition. > Are these actually level interrupts yes > and in order to clear them you need to poke some other register? to clear individual interrupt event you have to write corresponding 1b bit into that cause register. so if interrupts events BIT(24), BIT(16) and BIT(17) happened and BIT(24), BIT(25), BIT(26), BIT(27) and BIT(16) are unmasked then CPU receives two interrupts (one for intx:24-27 and one for err:16). kernel will call interrupt handlers for both intx and err (possible also in parallel if it unmasked on different CPUs) and each handler just clears events which process. So writing BIT(16) into cause register clears only event 16 and all other (24-27, 17) are still active. And level interrupt (the correct one intx or err) is then triggered again. > > + /* > > + * Old DT bindings do not contain "error" interrupt > > + * so do not fail probing driver when interrupt does not exist. > > + */ > > + port->error_irq = of_irq_get_byname(child, "error"); > > + if (port->error_irq == -EPROBE_DEFER) { > > + ret = port->error_irq; > > + goto err; > > + } > > + if (port->error_irq <= 0) { > > + dev_warn(dev, "%s: interrupts on Root Port are unsupported, " > > Maybe that should be "Error interrupts on Root..." ? > > Andrew >From PCIe Root Port point of view, it can be _any_ interrupt which can PCIe Root Port (as PCI device) reports (it does not have to be PCIe AER - error). Without this support PCIe Root Port cannot trigger or generate any interrupt. Note that from PCIe point of view, this Marvell Root Port never generates INTx interrupt. INTx interrupts are generated only by endpoint devices. Marvell Root Port reports all events via those _custom_ Marvell interrupts triggered by "error" source. So "error" here means "Marvell error", not "PCIe error" (e.g. PCIe AER). For example also PME events are reported via this "error" source. And PME is not error. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel